Image403

Stan bieżący nmn	■ C/=0		Ci-1
	Stan następny Wf X/ Y( 7/	Ci-1	Stan następny W/X/Y/Z/	CH
0 00 0	0 0 0 0	0	0 10 1	0
0 0 0 J	00 0 0	1	010 1	1
0 010	00 0 1	0	0 110	0
00 11	0 00 1	1	0110	1
0 100	0 0 10	0	0 111	0
0 10 1	00 1 0	1	0 111	1
0 110	00 1 1	0	1 00 0	0
0 111	0 0 11	1	10 0 0	1
10 0 1	0 100	1	100 1	1

JM

Jwjjwf

^Jxi,Kxi

\Y/?i

00 01 11 10 U o u 01 00

C/*0<

W/

^W,Xi \ 00 01 11 10

Cr O-

CM

00	00	00	00
00	00	00	00
01	01
00	00
00	00	10	10
00	00	00	00

IyMyi

00 01 11 10

Ci‘!

00	00	00	00
0/	01	01	01
10	10
00	00
00	00	01	01
10	10	10	10

JziJzf

C_H

mc

Y,Zf

JM

00 Ot 11 10

CfO<

CM<

0	■1	1	0
0	1	1	0
0	1
0	1
0	1	1	0
0	1	1	0

^W1^X '¹, \ 00 01 11 w

CM<

cm<

00	00	01	01
10	10	00	00
00	00
00	00
10	10	01	011
00	00	00	00

^=0

Rys. 4.473. Przetwornik szeregowy BCD/BIN a) tablica stanów, b) tablice Kamaugha, c) schemat logiczny

^Wi^xi \ 00 01 11 10

Ci‘0<

Ci*1<

00	01	00	10
00	01	00	10
00	01
10	00
10	00	01	00
10	00	01	00