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CIRCUIT CELLAR
®
Issue 144 July 2002
5
Driving the NKK Smartswitch
Part 1: Configuration and Software
Short Solutions
Build a Graphics LCD Bias Supply
AVR MCU-Based AC Phase Controller
An 80C31-Controlled Power Supply
RoCK Specifications
Part 4: Tying Up Loose Ends
Dealing With Motor Control Dead-Time Distortion
Starting Down the Pipeline
Part 2: The Long and Short of It
I
I
ROBOTICS CORNER
Extreme OSMC
Part 2: The Modular OSMC Brain
I
APPLIED PCs
Building a Modular Programming Platform
Part 1: The Program Module
I
SmartMedia File Storage
Part 2: Directory Entries
I
SILICON UPDATE
Eight Isn’t Enough
24
COLUMNS
ISSUE
Task Manager
Jennifer Huber
Reliable Information
New Product News
edited by John Gorsky
Advertiser’s Index
August Preview
Priority Interrupt
Steve Ciarcia
Like Avoiding a Bus
6
8
11
94
96
144
30
46
70
78
12
20
34
52
42
FEA
TURES
60
66
here would we be without reliable displays?
Having immediate access to data readouts is not
only useful, it’s crucial in many applications. For
instance, quick and concise messages relayed for medical
equipment can save lives. The ability to easily check on your home automa-
tion system can help you protect your family and home. The benefits of
decent graphics displays are obvious in a plethora of applications.
This issue contains articles about a few that we’re sure you’ll find interest-
ing. After seeing the ads, Aubrey Kagan decided it was time to explore the
capabilities of the Smartswitch from NKK Switches. He also wanted to make
use of the PSoC from Cypress Microsystems. The Smartswitch is a single-
pole switch that’s normally open. An LCD activates the switch. The results of
the project definitely put the Smartswitch as well as the PSoC in favorable
light. Working with Aubrey’s source code, you can test them yourself.
For further reading on graphics displays, turn to page 42. Keeping tabs on
systems built with PIC devices can get annoying when you have to rely on
either LEDs or seven-segment displays. But, after reading about Peter Chia’s
project, you’ll forget your notion of having to accept the standard way of doing
things. What about building an LCD controller for PIC devices? Another plus
is that Peter’s project uses only a few parts, so expenses are down.
You can save some money with Brian Millier’s suggestions, as well. Using
an inexpensive microcontroller, he tackles how to maintain desirable display
contrast over a range of temperatures. The key to success is stabilizing the
bias. With an AVR micro, Brian manages to keep the bias stable yet variable.
But, he doesn’t stop there. In addition to the LCD solution, Brian also discuss-
es an AVR microcontroller-based AC phase controller.
So, throughout this issue, you get a healthy dose of display-related materi-
al. The articles talk about solutions to typical problems, which are always help-
ful, as well as introduce you to a new LCD module that might pique your inter-
est. The common thread between Brian and Peter’s applications is giving you
ways to save money, obviously another benefit that’s always welcome.
In this issue, you’ll also find articles that cover a variety of topics other than
graphics and video. A frequent contributor, George Novacek, is back with
instruction on how to tame transients. If you’re interested in improving your
motor control, you’ll want to read Ross Bannatyne and Dave Wilson’s expla-
nation of how to handle distortion caused by dead time. They will impress you
with their inexpensive solution that enables a quiet, smooth-running motor.
Also, turn to page 50 for the fourth and final installment of “RoCK
Specifications,” by Joseph Jones and Ben Wirz. The series is a step-by-step
analysis of the RoCK, Joseph and Ben’s winning project from the Design
Logic 2001 contest sponsored by Atmel. The wrap-up covers the discrete
motor driver, the host interface to the RoCK, and how to create a new user-
programmed task.
6
Issue 144 July 2002
www.circuitcellar.com
CIRCUIT CELLAR
®
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Circuit Cellar® makes no warranties and assumes no responsibility or liability of any kind for errors in these programs or schematics or for the
consequences of any such errors. Furthermore, because of possible variation in the quality and condition of materials and workmanship of read-
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Reliable Information
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PC/104 ETHERNET LAN ADAPTER
The PC104-ELC is a 16-bit high performance
Ethernet LAN card. Its features include –40°C to 85°C
extended operation and full compatibility with IEEE
802.3 standards. The card delivers full-duplex Ethernet
data transmission at speeds up to 10 Mbps.
The PC104-ELC automatically detects whether it is
connected to an 8-
or 16-bit system.
The card has a
built-in RJ-45 con-
nector, 10Base-T
transceiver, and
optional BNC con-
nector support
10Base-2. It can be
installed under
PnP and jumper-
less methods or
jumper selection.
This adapter is fully NE2000-compatible. It comes
with drivers that support network operating systems
OS/2 LAN, Novell NetWare, and Microsoft LAN
Manager.
The PC104-ELC costs $159. Volume discounts for
OEM and distributors are available.
Radicom Research, Inc.
(408) 392-9688
www.radi.com
NEWS
8
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
NEW PRODUCT
Edited by John Gorsky
UNIVERSAL DEVICE PROGRAMMER
The Model 869 is a universal stand-alone programmer
designed to program chips while connected to a comput-
er or in the field without the use of a computer. The
Model 869 uses B&K Precision's device libraries, which
support PROMs, EPROMs, PLDs, and microcontrollers.
An extensive line of socket adapters to interface with
PLCC, SOIC, TSOP, DIP, TQFP, SSOP, PSOP, or QFP
devices is also available.
After its setup, the
Model 869 can be
taken into the field
and used as a stand-
alone device.
The Model 869
comes with a 48-pin
ZIF socket and offers
buffer features
including erase, ran-
dom data fill, fill
block, copy block, move block, swap block, buffer print,
find text, replace text, 8- and 16-bit view modes, go to
address, checksum calculator, and a standard parallel
printer port interface.
The Model 869, with a library, costs $995. It comes
with software, AC adapter, and parallel cable.
B&K Precision Corp.
(714) 237-9220
www.bkprecision.com
THERMALLY ENHANCED MOSFETS
The SUM110Nxx and SUM85Nxx TrenchFETs are
power MOSFETs in a thermally enhanced D2PAK pack-
age. They enable a low level of thermal resistance and
are capable of handling 29% more current than the con-
ventional D2PAK.
The new n-channel 40- to 200-V TrenchFETs are
designed for use in automotive applications, including
motor control, ABS, electric power steering, and 12- and
42-V Boardnet applications. Additionally, they work in
communications applications, including primary side
switching in the isolated DC/DC converters used in
servers, routers, and networks.
Compared with conventional D2PAK devices, the
new SUM series offers up to 29% higher maximum
current (110 A), 75% higher power dissipation (up to
437.5 W), and on-resistance as low as 2.3 mW. Thermal
resistance is as low as 0.4°C per watt, which is 33%
lower than in standard D2PAK devices. As a result, the
devices can handle higher current and more power, or
run cooler while handling the same amount of current
and power. Select D2PAK TrenchFETs in the series fea-
ture a maximum junction temperature as high as
200°C, an improvement of as much as 14% over the
standard D2PAK.
The SUM110Nxx and SUM85Nxx cost $2.17 in
100,000-piece quantities.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
9
NEWS
NEW PRODUCT
KEYBOARD EMULATOR IC
The Easy Input is an IC designed to allow the transfer
of ASCII data into keyboard-based PC programs.
Incoming data can be sent directly to applications via a
USB cable as if the data were being typed on a keyboard.
The device uses the standard USB keyboard drivers
included with Windows 98 and greater operating systems
and does not require any special software to operate.
The Easy Input was designed for ease of use from an
engineering perspective. Standard ASCII and supplemen-
tal characters are placed on an 8-bit bus and clocked
into the device. On the 24-pin versions, Shift, Alt, and
Ctrl lines are also available. These lines allow you to
produce almost any signal that can be created on a key-
board. The device requires only a resistor, resonator, and
cable to operate.
The device is available in DIP,
SOIC, and quarter-size outline
packages. The Easy Input is priced
at $6.83 in 1000-piece quantities.
Radovan Robotics
(805) 375-7059
www.radovan.org
FOUR-AXIS MOTION CONTROL CARD
The new PPCI7443 is an advanced four-axis motion
control card that allows control of stepper motors or ser-
vomotors. The unit incorporates a PCL6045 control chip.
The PPCI7443 offers 32-bit PCI bus plug-and-play
capability. It features a maximum output frequency of
6.55 Mpps, trapezoidal and S-curve motion profile capa-
bility, and the ability to change speed and position on
the fly. Any combination of two axes can be used for cir-
cular interpolation, or two, three, or four of the axes can
be used in linear interpolation.
The device offers 13 home return modes, a 28-bit
up/down counter for incremental encoder feedback, and
simultaneous start/stop motion on multiple axes. The
software incorporates an MS-DOS C/C++ programming
library, Windows 95/98/ME/NT/2000 DLL, and a test
monitor, and supports a maximum of 12 PPCI7443 cards.
The PPCI7443 costs $650. For an additional cost, a
100-pin cable and a junction
board are available.
Nippon Pulse Motor Co., Ltd.
(540) 633-1674
www.pulsemotor-usa.com
Use the Cypress PSoC
™
instead of an MCU for
more flexibility, fewer parts and lower cost.
The versatile PSoC
™
Programmable System-on-Chip
™
microcontroller, winner of EDN magazine’s Innovation
of the Year Award in the 8- and 16-bit microcontroller
category, is the world’s first MCU that lets you custom
configure the exact part you need.
Graphically select, place, and interconnect
the peripherals you want and adapt the
architecture with PSoC Designer
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Dynamically reconfigure a single PSoC
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8-bit PWM
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Cypress, PSoC, Programmable-System-on-Chip, and PSoC Designer are trademarks of Cypress Semiconductor Corporation. ©2002 Cypress Semiconductor Corporation. All other trademarks are the property of their respective owners.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
11
Problem 5
—
A full adder is a circuit with three
inputs and two outputs, and the output is a 2-bit
binary number that gives the number of ones on
the inputs. Can you come up with a circuit using
only full adders that can count the number of ones
on 15 inputs?
Contributed by Dave Tweed
Problem 6
—
Now suppose you want to know if
there are more than
N
ones on the inputs, where
N
is presented as a 4-bit binary number. Can you
add this functionality using just full adders (with
perhaps some inverters)?
Contributed by Dave Tweed
Problem 7
—
For the circuit shown below,
VCC = 15 V, hFE(min) = 30, and ib = 100 µA.
Find the minimum value of RL that will ensure
saturation operation.
Contributed by Dave Tweed
Problem 8
—
What is “comfort noise”?
Contributed by Dave Tweed
Problem 1
—
The circuit shown below is
an adjustable output voltage regulator.
Assume that the basic op-amp is ideal.
Find the regulated output voltage V
O
.
Contributed by Naveen PN
Problem 2
—
A dynamic RAM cell that
holds 5 V has to be refreshed every 20 ms
so that the stored voltage does not fall by
more than 0.5 V. If the cell has a constant
discharge current of 0.1 pA, what is the
storage capacitance of the cell?
Contributed by Naveen PN
Problem 3
—
Prove that the basic resis-
tor-transistor logic (RTL) gate shown
below is a NOR gate.
Contributed by Naveen PN
Problem 4
—
In general, what is the
order of gate complexity relative to the
number of inputs to be counted?
Contributed by Naveen PN
What’s your EQ?
—The answers and 4 additional
questions and answers are posted at
www.circuitcellar.com/eq.htm
You may contact the quizmasters at
eq@circuitcellar.com
Te s t Yo u r E Q
+V
R2
V
O
R1
V
Z
–
+
V
CC
R
C
V1
Q1
V2
Q2
V
O
V
CC
= 15 V
R
L
R
B
ib
CIR
CUIT
CELLAR
12
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
he NKK
Smartswitch is a
single-pole, normally
open switch with an
LCD screen that serves as its activa-
tor. I have often looked at the adver-
tisement for the Smartswitch and
thought about how cool it would be to
use it. But where and how can the
Smartswitch be used? In this series of
articles, I’ll explain my answer to
those questions.
The switch head of the Smartswitch
consists of a 24 × 36 pixel LCD and
some rudimentary driver electronics
that drive one row at a time. Control
signals are required to shift out the
pixel state for each row, latch the
pixel states, and synchronize the first
line. In addition, the display has a
backlight that can be configured as
red, green, or yellow. I have tried to
make the display interface pixel
addressable to allow for the mixture of
graphics and text to be placed any-
where on the screen.
Obviously, a microcomputer is
needed to drive the display. I wrote
the software so that the user interface
is through a series of RAM locations.
This allows display access to an exter-
nal hardware interface such as a serial
or parallel driver (based on the micro-
computer’s capabilities) in a stand-
alone application or a concurrent task
resident on the microcomputer.
At this time, I am unaware of any
published projects that use a Cypress
PSoC microcomputer. However, I’m
sure this will change in the near future
as more users begin to appreciate the
advantages of the PSoC. The versatility
of its I/O configuration, the low cost of
its development tools, and the price
and performance of its peripherals
make it an extremely attractive option.
In addition, the PSoC is available in
DIP packages, which is great for low-
volume applications and debugging.
And that’s a plus for aging baby
boomers who have difficulty seeing the
pins on SMD devices, let alone con-
necting an oscilloscope probe to one.
THE LCD
The LCD is controlled row by row
with a 40-bit shift register. The first
four bits shifted out are invisible, but
they must be included in the shifting
process. Each pixel has been allocated
a number so that the software imple-
mentation can address a specific loca-
tion. You can see this allocation in
Table 1. The firmware display driver
creates a memory map where each
pixel maps to a unique bit in RAM. As
you’ll see, the map is continuously
output to the display by the drivers.
In order to economize on RAM, the
memory map is implemented as a 24 ×
5 unsigned character array (cMatrix
Driving the NKK
Smartswitch
t
Sure, the NKK
Smartswitch looks like
a cool device, but
how can you actually
use it? Aubrey found
the answer with a little
help from a Cypress
Microsystems PSoC
microcomputer. In this
article, Aubrey
describes the inter-
face to drive the
Smartswitch.
Aubrey Kagan
FEATURE
ARTICLE
Part 1: Configuration and Software
Visible pixels
Invisible pixels
Row 0
39
38
37
…
7
6
5
4
3
2
1
0
Row 1
79
78
77
…
47
46
45
44
43
52
41
40
Row 2
119
118
117 …
87
86
85
84
83
82
81
80
…
…
…
…
…
…
…
…
…
…
…
…
…
Row 22
919
918
917 …
887 886
885
884
883
882
881
880
Row 23
959
958
957 …
927 926
925
924
923
922
921
920
Table 1—The numbering of the pixels is arbitrary. Pixels 0, 40, 80, etc. are the first bits shifted out for each row.
CONTEST ENTRY
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
13
turn on. The driver also draws current
through the resistor on the near side,
so it must be capable of sinking the
total current. Note that each driver is
connected to a microcomputer output.
In this case, it’s connected to port 1,
bits 0 and 1.
As with all LCDs, it is important
to be able to adjust the viewing angle.
The Smartswitch requires a simple
interface with a potentiometer
between a supply, as you can see
demonstrated in Figure 1b. NKK rec-
ommends 9 to 12 VDC.
There are four control lines to set
the content of the LCD matrix. Data
is presented serially on the D
IN
line,
and clocked into the shift register on
the negative transition of the clock
signal SCP. In other words, for each
row of pixels, 40 bits are shifted into
the D
IN
line and clocked on the nega-
tive edge of SCP.
The contents of the shift register are
transferred to the pixel drivers on the
negative edge of the LP signal. The LP
signal is independent of the SCP sig-
nal, but must occur periodically with
minimal jitter or the display’s intensi-
ty will vary. NKK specifies a period of
0.7 to 1.2 ms, but I found that 1 ms
works best for this application.
The Smartswitch has an internal row
pointer that is incremented every LP
signal. This counter is reset by the
first line marker (FLM) signal, which
must be active (after LP has transferred
the line data) for the data of the first
row. There are no restrictions on pump-
ing the data out (subject to the maxi-
mum 2-MHz clock rate), so it can be
accomplished quickly. This gives the
processor some processing time until
it is necessary to toggle the LP signal.
[24][5] in the software). Obviously, the
first index is the row number and the
second refers to the column number.
Each bit in a byte is allocated to a
pixel as shown in Table 2.
The design of the Smartswitch
allows for multiple switches by link-
ing the 40-bit shift registers. Because
of the processor’s RAM limitations, I
have left room for only one switch
and one controller. I believe the road
map for the PSoC includes devices
with up to 1 KB of RAM, so it may
be possible someday to expand the
application. At any rate, the PSoC’s
low cost may allow for a multi-
processor solution because the
switch itself is around $50.
HARDWARE INTERFACE
The backlight of the LCD consists
of bicolor LEDs. When current passes
in one direction, the backlight color
is red; when it passes in the reverse
direction, the color is green.
Toggling from red to green at the cor-
rect frequency will trick your brain
into thinking the color is yellow.
The backlight is turned off when
there is no current.
As you can see in Figure 1a, a
resistor connects each side of the
LED to the same voltage supply.
Different LED colors have different
efficiencies. You can compensate for
this by programming a different cur-
rent for each direction.
The connections to the LEDs are
totally independent of the rest of the
control circuitry so this supply need
not be V
CC
. Each side of the LED back-
light is also connected to an open col-
lector driver. When active, the driver
will sink the current through the
resistor on the far side of the LED and
through the LED, causing the LED to
Port1_1
ULN2803
Port1_0
ULN2803
NKK
R1
R2
5
14
V
S
Figure 1a—With the backlight drivers, when port1_1 is high and port 1_1 is low, current flows through R1 and
from pin 5 to pin 14 and turns on the green LED. Note that the current will still flow through R2. The red LED will
be on when port1_0 is high and port 1_1 is low. Toggling at about 550 Hz will produce a yellow color. b—This is
the LCD viewing angle adjustment. I used 9 V
DC
for V
S
and 1 KB for VR1.
Listing 1—An endless loop is a simple form of cooperative multitasking. The project is broken into func-
tions and each function is executed sequentially. The function has total control (except for interrupts) and
must write the yield control back to this routine within a reasonable time.
while (1)
{
switch (cPhase)
{
case 0:
RefreshMatrix();
cPhase++;
break;
case 1:
Backlight();
cPhase++;
break;
case 2:
ProcessCommand();
cPhase++;
break;
case 3:
//Process();
cPhase++;
default:
cPhase=0;
break;
}
}
NKK
12
13
11
VR1
V
S
V
CC
a)
b)
an on-chip temperature sensor. On
the digital side, there are counters (up
to 32 bits) and pseudo-random num-
ber generators (up to 32 bits). In addi-
tion, there’s pulse width modulation
(up to 16 bits), UART, SPI, a CRC
generator, and timers (up to 32 bits).
Future additions may include an I
2
C
and USB modules.
It’s your job to supervise the alloca-
tion of these functions to the blocks
and to choose the I/O pins.
Remember, though, that the number
of available blocks will limit the num-
ber of functions you can implement.
Keep in mind that the PSoC is like
any other microcomputer—it’s not a
Designer allows you to choose
between peripherals and allocate them
to the analog and digital blocks on the
chip. The peripherals include multi-
channel A/D converters (up to 12 bits),
programmable gain amplifiers, com-
parators, D/A converters, filters, and
14
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
You can see the timing relation-
ships for this project in Figures 2a and
b. Most of the hardware interface is
achieved through peripherals that are
implemented on the PSoC. But before
I describe the peripherals, I’ll intro-
duce you to the general configuration
of the PSoC.
PSoC
Despite the risk of dampening your
enthusiasm, I want to make clear that
this family of devices (and the associ-
ated tools) is relatively new. As a
result, there are some minor bugs
and certain aspects of the documen-
tation have conflicting information.
All in all, some features of the user
interface and C compiler need
improvement. However, if you enjoy
the challenge of mastering a new
micro, especially one with the fea-
tures of the PSoC, then you’re going
to love this product.
Almost every microcomputer on
the market has a finite peripheral set
that may include a UART, A/D con-
verter, and timers. But if you want a
micro without the ADC, you’ll have
to change the device. Sometimes you
can get lucky and the pinout will be
the same, but you’ll still have to jug-
gle the features and often pay for ones
that you don’t need.
Fortunately, Cypress has taken a dif-
ferent approach. The PSoC has eight
digital blocks and 12 analog blocks.
Like a PLD, these blocks can be con-
figured to provide different functions,
so you can customize the microcom-
puter for the exact peripherals you
need. In fact, the peripherals can be
configured dynamically to share the
configuration blocks, making them
something like hardware subroutines.
The user interface, or PSoC
Designer, is available for free on the
company’s web site. The PSoC
Listing 2—The background routine waits for a signal from the timer interrupt, then it initiates the first byte of
transmission on the SPI block and prepares the pointer for the interrupt routine for the next four bytes or the
row. Every 24 lines the FLM signal is activated.
void InitiateRefresh (void)
{
RAMpnt=&cMatrix[0][1];
cRowCount=0;
//Initiate the transmission by writing the first byte. The
rest
get sent in assembler
PRT0DR |= FLM;
cByteCount=4;
//Update the display here
//Display();
SPIM_1_SendTxData(cMatrix[0][0]);
}
void RefreshMatrix (void)
{
if (cStatus & LP_DONE)
{
cStatus &= ~LP_DONE;
if (cRowCount<23)
{
cRowCount++;
RAMpnt=&cMatrix[cRowCount][1];
cByteCount=4; //sending four more bytes
SPIM_1_SendTxData(cMatrix[cRowCount][0]);
//Send first byte
}
else {
InitiateRefresh();
//Only update here
}
//Only get here every 1 ms, so you can use as basis of ms
timer
if (cFlashCount!=0)
{
cFlashCount--;
}
if (cYellowCount!=0)
{
cYellowCount--;
}
if (cCount!=0)
{
cCount--;
}
}
}
cMatrix[n][0]
cMatrix[n][1]
cMatrix[n][2]
cMatrix[n][3]
cMatrix[n][4]
Bit number
7
6
1
0
7
0
7
0
7
0
7
1
0
Row 0
39 38 … 33
32
31 …
24
23 … 16
15 …
8
7
…
1
0
Row 1
79 78 … 73
72
72 …
64
63 … 56
55 … 48
47
…
41
40
…
… …
…
…
…
…
…
…
…
…
…
…
…
Table 2—In RAM to pixel mapping, for example, the most significant bit of cMatrix[1][0] will map to pixel 79 and
the least significant bit of cMatrix[0][2] will map to pixel 16.
16
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
panacea. Before committing to a
design, take time to evaluate the
peripherals, especially the analog
blocks. The analog blocks are not rail-
to-rail, but rather they are 2.5 V (sup-
ply half-rail). That is, the analog zero
is considered to be at 2.5 V, and the
input signal may need to have a DC
offset applied.
When the function module is
placed and graphically configured,
PSoC Designer creates the code to set
up the registers needed to realize the
function. All of the configuration set-
tings are dynamic registers, so they
can be overwritten to change the con-
figuration. And this doesn’t have to be
as simple as changing the gain on an
amplifier, in fact, more complex
arrangements could be made.
Suppose you had a converter from
SPI to UART. It would be possible to
interface with an SPI peripheral,
gather the data, reconfigure the digi-
tal blocks to perform as a UART,
and then retransmit the data on dif-
ferent pins. The reverse would also
be possible.
Figure 2a—This is a row update. Although difficult to count here, there are 40 SCP pulses in five bursts between
each LP signal. Note the 1-ms update time. b—The FLM extends from before the first data bit to the trailing edge
of the LP signal. FLM becomes active before the first SCP transition for the row. You’ll see later that the LP will
trigger an interrupt that flags the background program. The FLM is set in the background program. The indicated
time is the time for the processor to get to the point in the program where the bit is set. Care must be taken to see
that the last of the 40 bits is shifted in before the next LP signal.
a)
b)
Listing 3—The terminal count on the timer module will generate an interrupt and output pulse every mil-
lisecond. A flag is sent in the interrupt routine to indicate to the background routine that the pulse has been
generated so that the next line can be shifted out. Note the software loop that delays the reset of the FLM
line. This happens every interrupt whether or not the FLM is set.
Timer8_1INT:
//place user code here
//set cStatus bit to indicate interrupt has happened
push
a
mov
a,01h
or
[_cStatus],a
//if requested, drop FLM
tst
[_cStatus],02h
jz
skip1
//delay so FLM goes to negative after LP
mov
a,48
skip2:
dec
a
jnz
skip2
and
[_cStatus],0fdh
//clear the bit
and
reg[PRT0DR],0feh
//clear the FLM
skip1:
pop
a
reti
352*5$03,&
352*5$03,&
352*5$03,&
352*5$03,&
352*5$03,&
ª6,1%$6,&
ª6,1%$6,&
ª6,1%$6,&
ª6,1%$6,&
ª6,1%$6,&
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18
Issue 144 July 2002
CIRCUIT CELLAR
®
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signal from an 8-bit timer that would
interrupt every millisecond. I took
the terminal count (TC) output
directly to an output pin to be used as
the LP signal. The width of the TC
signal is the same as the high period
of the input clock.
To drive the data and SCP lines, I
used an SPI master (SPIM) without the
receiver function. As expected, it’s pos-
sible to configure the edge and polarity
of the clock signal relative to the data
being shifted out. So, I thought I would
relieve the processor overhead by
allowing the hardware to shift eight
bits at a time. This called for proces-
sor intervention after every byte
under interrupt control. The only
are two internal prescalers available
for clocking functions, 24V1 and
24V2. The former is the internal 24-
MHz oscillator divided by a number
from one to 16. The latter will further
divide 24V1 by a number from one to
16. I set 24V1 to 16 and 24V2 to 15 in
order to generate a clock signal of
100 KHz with a counter resolution of
10 µs. All of these settings are set up
in a graphical user environment, part
of which is visible in Photo 1. PSoC
Designer then translates the settings
into code in a process that is transpar-
ent to the user.
I didn’t need many modules for the
implementation of the hardware
interface, so I decided to drive the LP
Currently, PSoC Designer does
nothing to enhance this. It allows for
one configuration and then it’s up to
you to create alternatives to overlay
these functions. Cypress has decided
that this feature is a competitive
advantage, so they have a new version
of their PSoC Designer in the wings
that will simplify this process.
Cypress produces three kinds of
documentation. The first is the stan-
dard datasheet, which at first glance
is somewhat bewildering because of
the variety of configuration options.
When you select a module in the
user interface, a datasheet for the
module appears on the screen. In
addition to samples of the code, the
datasheet reading includes all the
relevant registers and I/O points. As
your product is configured, the PSoC
Designer creates a third datasheet
specifically for that particular
arrangement so you have complete
documentation of your product.
All of this is available in an 8- to
64-pin package for about $5. A full
development environment that
includes C costs less than $300. And
you’d think they were paying me to
say this, but unfortunately they’re not.
MODULE IMPLEMENTATION
Let’s get back to the project at
hand. The PSoC does not need an
external crystal operating to within
±2.5% of the intended oscillator
value. This is because the internal
oscillator operates to within ±2.5% of
the intended value. The base frequen-
cy of the unit is 24 MHz, and the
timer/counter clock sources can be
derived from this. In fact, the digital
modules can work up to 48 MHz.
You can set a number of global
resources, but I only changed three of
them for this particular application. I
set the CPU clock to 12 MHz. There
Listing 4—The first byte transmitted from the SPIM module is initiated from the background program.
When the transmission is complete, an interrupt will be generated and program execution will be vectored
to this routine. This routine will fetch a further byte and transmit it until four more bytes have been sent.
After these five bytes have been transmitted, the routine does not send another byte, so the interrupt will
not occur again until the first byte of a new line is sent from the background routine.
SPIM_1INT:
//place additional SPIM interrupt level processing here
push a
push
x
call bSPIM_1_ReadStatus
;wait for SPIM done, rather than buffer empty
;because of taking FLM low, after all the data has gone
and
a,(SPIM_SPI_COMPLETE)
jz
SPIM_EXIT
//Have we transmitted five bytes (one from C call and four
continuing from there)?
mov
a,[_cByteCount]
jnz
SPIM1
//At this point, all 30 bits have been shifted out, so clear
FLM. reg[PRT0DR],0feh FLM must be high during LP, so set
the request.
or
[_cStatus],02h
jmp
SPIM_EXIT
SPIM1:
//Decrement count
dec
[_cByteCount]
mov
x,[_RAMpnt+1]
//Fetch address in matrix from LSB
mov
a,[x+0]
//Fetch data from address
//
mov
a,0ffh
call
SPIM_1_SendTxData
inc
[_RAMpnt+1]
//Although this is a two-byte address, it is an address in
RAM so it can never be greater than 0xff.
SPIM_EXIT:
pop
x
pop
a
reti
PSoC
P0_6
P0_4
P0_2
P0_0
NKK
SCP
D
IN
LP
FLM
9
10
8
7
27
26
25
24
Figure 3—The wire interface is simple. Note that the
pin numbers for the PSoC are for the 28-pin DIP.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
19
other information you’ll need refers to
the connection of the internal signals
to the output pins (see Photo 1).
Figure 3 depicts the simple wiring
for the microcomputer to the LCD
interface. The software for this project
is written in a simple fashion allowing
multiple tasks. Tasks are identified
and numbered as cPhases. The back-
ground routine in Listing 1 is included
in main.c. This extract is the heart of
the operation. RefreshMatrix is the
process that maintains the scan of the
display. It’s contained in Matrix.c, you
can see a portion of in Listing 2.
The interrupt of the 8-bit timer
occurs every millisecond. The PSoC
Designer cannot implement interrupt
routines in C, so this routine is in
assembler module Timer8_1INT.asm
(see Listing 3). Note how the PSoC
Designer has created the routine iden-
tifying where the user code should be
placed. When eight bits have been
shifted out of the SPI controller an
interrupt is generated, vectoring to the
code in SPIM_1INT.asm (see Listing 4).
The software is connected as follows.
When a timer interrupt occurs, a flag
(LP_DONE) is set in cStatus. The
processor tests this flag within Refresh-
Matrix. If set in cStatus, the LCD line
pointer (RAM address cRowCount) is
SOURCES
NKK Smartswitch
NKK Switches Of America, Inc.
(480) 991-0942
Fax: (480) 998-1435
www.nkkswitches.com
RESOURCES
Cypress Microsystems, “CY85C-
25xxx/26xxx,” CMS 10002A-R.13.
NKK Switches of America,
Inc.,“NKK Programmable LCD
Switch Data Sheet,”
www.nkkswitches.com.
Photo 1— Pins are allocated either by clicking on the graphic outline of the package or by modifying the table in
the bottom left window. Those pins that are not allocated to the user modules may be used as standard micro-
computer I/O.
Aubrey Kagan (P.E.) has 25 years
of experience in the design of
electronic industrial interfaces.
He has a BSEE from the Technion,
Israel Institute of Technology and
an MBA from University of the
Witwatersrand. His diverse design
experience ranges from projects
that operated two miles under-
ground in a mine to 600 miles
above the earth in the
International Space Station. He is
currently a senior design engineer
for Weidmuller Canada. You may
reach him at akagan@weid-
muller.ca.
tested and when it’s greater than 24
(number of lines on the screen) the
process is refreshed and the FLM line is
set high. In contrast, if it’s not greater
than 24, the counter is merely incre-
mented. In either case, the first byte
of the line is sent to the SPIM master
and a pointer is initiated (RAMpnt)
for use in the SPIM interrupt routine
along with the number of bytes left to
be transmitted (cByteCount = 4). I
prefer to do this in C because it
allows for easy access to the array.
When the SPIM interrupt occurs, the
processor checks to see if there are any
bytes left to transmit (in cByteCount).
If a byte remains, the processor fetch-
es it by RAMpnt, transmits it, and
decrements cByteCount. If there are
no bytes left, the processor exits the
interrupt. Additional SPIM interrupts
will not occur until the RefreshMatrix
routine writes the next byte after the
next LP interrupt.
At the next timer interrupt, the
routine sets the LP_DONE flag once
again and clears the FLM line after
the output signal becomes low. It
always clears the FLM signal whether
or not it’s set. The routine stretches
the point where the FLM signal is
cleared through a software timer loop.
Take care when doing the background
loading of the processor because the
LP_DONE flag must be seen with
enough time for the 40 bits to be
transmitted before the next LP signal
(see Figures 2a and b).
Now you know how to configure
the peripherals of the PSoC to imple-
ment the hardware interface to the
NKK Smartswitch. In addition, you’ve
seen the basic software flow to shift
data out of the shift registers con-
tained within the Smartswitch. In
Part 2 of this series, I will show you
how to add functions for a character
generator. I will also describe a user
interface that will allow the display of
graphics and text and the ability to
place them anywhere on the screen.
I
20
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
raphic LCD
panels require a
stable negative volt-
age source for bias pur-
poses, termed V
EE
. Depending on the
size of the display, the voltage required
could be between –7 and –15 V, but
the current draw is miniscule.
Because this bias sets the contrast of
the display, it must be stable but vari-
able over a small range to maintain
good display contrast at various tem-
peratures. It’s also useful if the V
EE
source can be varied smoothly under
computer control. Although I’ve used
chips designed specifically for this
purpose, I thought I could build a less
expensive version using the smallest
member of my favorite microcon-
troller family, the Atmel AVR family.
The ATtiny12 microcontroller used
here costs less than $2 in unit quanti-
ties (see Figure 1).
A fly back converter made up of
transistor Q1, inductor L1, Schottky
diode D1, and filter capacitor C2 gen-
erates the negative voltage. The drive
for transistor Q1 is supplied by port
B2 of the ATtiny12 using a pulse-fre-
quency modulation scheme. Basically,
a 10-µs active-low pulse from the
ATtiny12 turns on Q1 and transfers
roughly as much energy into L1 as it
can absorb. Q1 then is shut off for
about 50 µs, which allows L1 to dump
this energy through D1 into C2. The
collapsing magnetic field induces a
voltage opposite to that of the charg-
ing current, so a negative voltage is
generated across C2.
The voltage is regulated with the
help of the ATtiny12’s internal analog
comparator. I’ve configured the analog
comparator to use an internal 1.2-V
band-gap reference as the positive
comparator input. The comparator’s
negative input is connected to port B1.
This pin acts as a summing junction
made up of the negative bias output
voltage and the V
CC
supply, the pro-
portions of which are adjustable by
R4, the voltage adjust potentiometer.
For now you should ignore R3.
The ATtiny12 is constantly in loop
checking the analog comparator and
sending a 10-µs pulse (followed by a
50-µs rest) whenever it senses that the
bias voltage is dropping below the
user-specified set point. This action
maintains the charge on C2 and keeps
the output well regulated. Because of
Short Solutions
g
When Brian proposed
these two straightfor-
ward, simple fixes, we
thought it was a great
idea to combine them
as a section of quick
solutions. Read on for
inexpensive ways to
control a high-current
resistive load and
how to build a graph-
ics LCD bias supply
with Atmel products.
Brian Millier
FEATURE
ARTICLE
Figure 1—Here’s the Graphic LCD V
EE
generator with an Atmel ATtiny12 microcontroller.
Build a Graphics LCD Bias Supply
AVR MCU-Based AC Phase Controller
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
21
is essential to filter out any false trig-
gering that might otherwise occur
from noise/spikes on the AC line.
The ’2313 receives a rising-edge
INT0 interrupt just prior to the zero
crossing. First, the ISR turns off the
triac drive by setting the port D4 pin
high. It clears Timer1 and loads
Timer1’s Output Capture register with
the necessary delay time to produce
the desired output power. Later in the
AC cycle when Timer1’s value match-
es the Output Capture register, a
Timer1 output capture interrupt is
executed. The interrupt drops port D4
the high switching speed, C2 can be a
small value capacitor, but it should be
tantalum for a low noise output.
To achieve the computer-controlled
fine-tuning of this bias supply, the
ATtiny12 also implements an 8-bit
PWM function at port B4. After fil-
tering the PWM waveform, a voltage
proportional to the duty cycle of the
PWM waveform appears across C4.
Using a high-value resistor for R3
(680 K
Ω
) and adding this current into
the summing junction at PB1 allows
fine-tuning of the bias to be achieved.
Generally a
±
20% fine-tuning range
AC phase control is a well-estab-
lished way of controlling high-current
resistive loads such as lights and
heaters. You can achieve this under
computer control by using a simple
AT90S2313 AVR microcontroller to
convert user-specified power levels
into properly timed trigger pulses to
fire a high-power triac device.
Inexpensive 15-A triacs can easily
handle power levels of 1800 W.
To accomplish this, the ’2313
microcontroller must sense the power
line zero crossing, which occurs at a
120-Hz rate. Power control is achieved
by triggering the triac after some spe-
cific delay from this zero crossing. No
delay would result in full power, and a
delay approaching 8.33 ms (one half-
cycle of the AC line waveform) would
result in little power being delivered
to the load. The exact relationship is
described later.
Accurate triac trigger pulses can be
generated by a ’2313 AVR microcon-
troller using an Interrupt Service
Routine (ISR) prompted by the INT0
interrupt. INT0 is connected to a
MOC5009 optocoupler that’s fed by
the otherwise unused negative half of
the power supply’s bridge rectifier. In
this configuration, the MOC5009’s
output will be low for the entire AC
line cycle time apart from a short
interval surrounding the zero crossing.
The MOC5009 incorporates a Schmitt
trigger in its detection circuit, which
is sufficient to provide optimum
contrast over a commercial tempera-
ture range, but you can tailor the
value of R3 to suit a particular LCD
application.
The PWM duty cycle is varied in
response to signals present at the step
and dir inputs. The Step input pulse
must be at least 15-µs long to guaran-
tee recognition. The high/low value
present on the DIRECTION pin at
the time of the pulse will determine
whether the PWM duty cycle increas-
es or decreases. You can specify
256 discrete PWM duty cycle values
within the
±
20% fine-tuning range.
Another important feature is the
delayed turn-on. LCD panels require
that the V
EE
supply switch on later
than V
CC
. For the LCD panel I was
using, this delay was 20 ms or
greater. The program code running in
the ATtiny12 has a delay loop at the
beginning to accomplish this. The
actual delay time could be changed by
the end user, if necessary, by changing
a program constant.
The source and object code for this
circuit can be found on the Circuit
Cellar
web site.
I
AVR MCU-Based AC Phase Controller
and results in a gate pulse being sent to
the triac, which turns it on. The triac
gate drive is provided by the MOC3009
optocoupler, which is specifically
designed for triac triggering.
A three-pole DIP switch sets the
device address for the controller to a
value between zero and seven, allow-
ing up to eight controllers to be inde-
pendently controlled using a single
RS-232 signal.
Timer1 is clocked by the 4-MHz
system clock that is prescaled by 64,
which results in it being incremented
every 16 µs. Because the INTO inter-
Figure 2—This a complete circuit diagram of the AT90S2313.
22
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
rupt occurs just prior to the zero cross-
ing, I measured that a delay of 29 (of
the 16 µs clocks) was needed to pro-
duce the gate pulse at the zero crossing.
Similarly, the maximum delay needed
for zero power was 578 clocks. Figure 1
shows the complete circuit diagram.
The mathematical relationship
between a traic’s firing angle and the
percentage of power delivered (0% to
100%) is shown in Figure 2. This rela-
tionship seemed too complex for the
small microcontroller to calculate on
the fly. Therefore, the power range
was broken down into three straight-
line segments and a simple linear
interpolation routine was performed.
The routine required one multiplica-
tion and one subtraction. As you can
see, this does not result in too great
an error from the ideal firing angle.
I patterned the controller’s com-
mands as a subset of the MIDI com-
mand protocol used by electronic
musical instruments. The two con-
troller functions are implemented
using commands corresponding to
MIDI Control Change messages.
BX
H
07 pp is the power level, which
corresponds to the volume level in
MIDI. Here, X is the controller device
number (0–8) and pp is a 1-byte value
representing the percentage of power
delivered (0 to 100 V).
BX
H
01 dd is the ramp time, which
corresponds to the modulation wheel
in MIDI. Here, X is the controller
device number (0–8). dd is a 1-byte
value representing the ramp time (in
seconds) for a 0% to 100% power
level change (0–127).
Setting the ramp time equal to zero
makes the controller switch power
levels immediately upon receipt of a
power level command. Alternately, set-
ting a ramp time to greater than
zero adjusts the controller to ramp
from its current power level to a
new power level upon receipt of
subsequent power level commands.
Because the ramp time parameter is
defined as the time it takes to ramp
from 0% to 100%, proportionately
less time is needed for smaller
power level changes to occur.
All controllers, regardless of
their device number (as set by the
DIP switch), will respond to com-
mands sent to device eight. This
allows you to control numerous lamps
simultaneously. The controller’s
firmware is written using the BAS-
COM-AVR compiler. The data rate is
set to 9600 bps. If you replaced the
RS-232 level shifter with the standard
MIDI optocoupler input circuit and
changed the data rate to 32,500 bps,
you could use this controller for MIDI
applications instead of RS-232.
You may download the source and
object code for this circuit from the
Circuit Cellar
web site. As with near-
ly all members of the Atmel AVR fam-
ily, this is a flash memory device and
is readily programmable. For more
information, I provided details of a
simple programmer in my previous
article, “My fAVRorite Family of
Micros” (Circuit Cellar 133).
I
SOURCES
AT90S2313 AVR, ATtiny12
Atmel Corp.
(408) 441-0311
Fax: (408) 436-4200
www.atmel.com
BASCOM-AVR compiler
MCS Electronics
31 75 6148799
www.mcselec.com
Brian Millier is an instrumentation
engineer in the Chemistry Department
of Dalhousie University in Halifax,
Canada. He also runs Computer
Interface Consultants. You may reach
him at brian.millier@dal.ca.
100
80
60
40
20
0
0
30
60
90
120
150
180
g
g
% P
o
w
e
r
Phase angle
— Actual
— Fitted
Figure 1—You can see the relationship between the percent-
age of power delivered and the triac firing angle.
SOFTWARE
902 Waterway Place | Longwood, FL 32750 | 800·635·3355 | 407·262·0066 | Fax 407·262·0069
Visit our website @ www.micromint.com to see our complete line of OEM Solutions.
The embedded controller that’s out of this world.
When engineers working on NASA’s Space Shuttle imagined the right embedded controller for their critical payload
experiments, they turned to the one supplier with more solutions than any other supplier of embedded controllers in
the world — Micromint.
With over 250,000 controllers in the marketplace, Micromint has been providing innovative, turn-key solutions to the
OEM market for over twenty years- from design through production, as well as packaging and shipping the final product.
Our broad line of embedded controllers and turn-key solutions can turn your imagination into reality.
24
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
very engineer,
technician, and
hobbyist needs a sta-
ble power supply to
power up the circuits they’re working
on. However, it would be nice if you
could vary the potential to accommo-
date many circuits. It also would be
pleasant if you could vary the current
supplied to the circuit, which would
limit the power delivered in case
something is wrong. The circuit fea-
tured here is an 80C31-controlled
power supply that has voltage and
current limits that you can change to
suit your needs (see Photo 1). Its volt-
age ranges from 0 to 22 V, and its cur-
rent ranges from 0 to 2.5 A.
In most power supplies, you turn a
knob to adjust the voltage and current.
The 80C31 CPS, however, has a keypad
for entering the voltage and current,
as well as Set Voltage and Set Current
buttons so you can change the voltage
and current immediately by moving
through a few menus. Additionally,
you can monitor the voltage and cur-
rent delivered by the power supply
with the 80C31 CPS’s built-in volt-
meter and ammeter. The voltage and
current is displayed using an LCD.
CIRCUIT DESCRIPTION
The brain of the circuit is the popu-
lar 80C31 microcontroller, which is
the version of the 80C51 without
ROM. The 80C31 is a widely available
(it’s produced by several manufactur-
ers) and high-quality microcontroller
for embedded design considering its
instruction set and price.
The 80C31 has 128 bytes of RAM,
two external interrupt pins, two
timer/counters, and serial ports (see
Figure 1). It has 32 I/O pins, but does-
n’t have ROM, so some of the ports
(namely ports 0 and 2) are used for the
address bus and data bus. A few of the
pins of port 3 are also used to inter-
face to other devices like ADCs and
DACs. The pins serve as read and
write signals for proper bus operation
like the read cycle and write cycle. So,
after interfacing the ROM, ADCs, and
DACs, you’re left with 14 I/O pins.
Port 1 is used to interface and read
the keypad. Some of the pins in port 3
are used for the Set Voltage and Set
Current buttons, while others are used
to control the relay and analog switch-
es to read the voltage and current to
be fed to the ADC.
U2 74HC373 is a transparent latch
(see Figure 2). It’s used to obtain the
address because the address bus and
data bus are multiplexed on port 0 to
conserve pins coming out of the IC.
The address is obtained after the
address latch enable, or ALE, is assert-
ed. U3 is an 8 KB × 8 UV EPROM
(27C64) that stores the program that
sets the voltage and current and reads
the ADC. I chose the 27C64 EPROM
because it’s inexpensive, available, and
the firmware will fit in it. You can
actually use larger EPROMs like the
27C512, but they’re a waste of space,
money, and time because you’ll have
to wire the added address pins. The
4K × 8 EPROM can also be used but
it’s hard to obtain.
An 80C31-Controlled
Power Supply
e
Even if you’re a
novice, it’s pretty easy
to control the power
supplied to the cir-
cuits you’re working
on. In this article,
Noel introduces us to
a 80C31-controlled
power supply, which
is a circuit that
enables you to moni-
tor and alter voltage
and current levels.
Noel Rios
FEATURE
ARTICLE
Photo 1—Take a look at the front panel of the 80C31-
controlled power supply.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
25
to the three-bus system using four
NAND gates. Because the LCD is
slow, the busy flag is read after an
operation to see if it is busy or not.
Failing to poll the busy flag will result
U4 ADC0820 is a successive approx-
imation analog-to-digital converter
that converts an analog input voltage
to an 8-bit equivalent value. It’s fast
and provides the necessary handshak-
ing pins to interface to the three-bus
architecture without glue logic. U4
ADC0820 also converts the analog
voltage to an 8-bit equivalent value.
U7 CD4053 is a triple one-of-two
switch. It is used to select between the
voltage and current. Wondering why I
said current? Using a high-side current
detector, the current flowing through a
sense resistor is converted into a suit-
able voltage to be read by the ADC.
U5 and U6 AD7524 are digital-to-
analog converters. They convert a dig-
ital value to an equivalent analog cur-
rent. They’re chosen because they pro-
vide the hardware needed to interface
to the system bus. In addition, they’re
fast and behave like RAM memory.
U9 LM358 and the adjustable resis-
tors form a pair of current-to-voltage
converters. U8 74HC138 is an address
decoder that’s used to access the ADC,
DAC, and LCD. The MOVX memory
space is divided into 8 parts of 8 KB
each. I used this scheme so that you
can also insert an 8-KB RAM just in
case it’s needed. Actually, the MOVX
instruction generates the read and
write signals whenever it’s executed,
so you can read and write to external
devices connected to the bus.
LCD1 is an LCD module based on
the popular HD44780. It’s interfaced
V
CC
V
SS
RAM
address
register
RAM
B
register
ACC
Port 0
drivers
P0.0–PO.7
Port 2
drivers
P2.0–P2.7
Port 0
latch
Port 2
latch
ROM/EPROM
Stack
pointer
TMP2
TMP1
ALU
PSW
SFRs
timers
Program
address
register
Buffer
PC
increment
Program
counter
DPTRs
multiple
16
8
Port 1
drivers
P1.0–P1.7
Port 3
drivers
P3.0–P3.7
Port 3
latch
Port 1
latch
Timing
and
Control
Instr
uction
register
*PSEN
ALE*PROG
*EAV
PP
RST
Oscillator
XTAL1
XTAL2
PD
Figure 1—The 80C31 has 128 bytes of RAM, two external interrupt pins, two timer/counters, and serial ports.
Figure 2—In the digital portion of the power supply, U2 74HC373 is a transparent latch used to obtain the address.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
27
79L05 serve as pre-regulators for the
voltage references. U2 7805 is the
voltage regulator for the logic circuit.
Note that the 1-A variety is used
because this also powered the EPROM
emulator used during development of
the firmware, which consumed a great
amount of electricity.
C2, C3, and C6 are filter capacitors
used to make the regulators more sta-
ble. R5, R27, and D4 LM336-2.5 form
the ADC voltage reference. The vari-
able resistor R27 trims the voltage to
2.55 V. R20 and D14 LM336-2.5 form
the voltage reference needed by the
DAC ICs. R26 is used to bias the
Darlington transistor, which is a
series pass element comprised of Q5
and Q6, which form the Darlington
transistor. The series pass element
acts as a variable resistor to change
the output of the power supply.
R10, R21, R22, R23, R24, and U7
MC4741 act as a high-side current
detector. Essentially, it’s a subtractor
that gives a voltage in proportion to
the ratio of the resistor and voltage
difference. The current moving across
R10 produces a voltage drop that’s
detected by the subtractor, and then
it’s amplified according to the ratio of
the resistances. A 2.5-A current pro-
duces a 2.5-V potential. This potential
in erratic operation or no display at
all. In order to interface the LCD
properly, you’ll often need two signals
at one time to perform an operation.
Namely, the decoded signal like a
chip select signal and the read signal
for a read operation. The two signals
must be turned on at the same time
for a proper read operation. The same
principle applies to the write cycle.
C9 and R4 form the RC time delay
for proper reset. The specifications
require several clock cycles during
which the reset is high until the clock
generator is stable. D2 serves to dis-
charge the capacitor after the power is
removed. C5 to C14 serve as an imme-
diate source of voltage because the sup-
ply rail drops as a result of the internal
switching of the transistors. The volt-
age drop is caused by the inductances
in the wire or traces of the PCB. And
as you know, the current cannot
change immediately when there is an
inductor present in the circuit.
Rectifier diodes D2, D3, D5, and D7
1N5400 convert alternating current to
pulsating DC (see Figure 3). C1 filters
the pulsating DC to smooth DC. C7,
C8, D17, and D18 are configured as a
charge pump that serves as a source
for the negative voltage needed by the
high-side current detector.
Zener diode D1, R1, R6, and Q1 pro-
vide a constant current source for the
thermal sensor. Q8 serves as a ther-
mal sensor and limits the base current
to the series pass transistor after it
reaches a certain temperature. The
collector current increases as the junc-
tion temperature increases even if the
base current is constant. This works
in theory, but it has not been tested
because I don’t have a themocouple
themometer. I did use, however, a 4
″
×
4
″
heavy-duty heatsink.
D12, D13, C4, and C5 form a split
supply power source that’s used to
power the logic circuit, ADC refer-
ence, and the negative supply for the
DAC reference. U1 78L05 and U3
Photo 2—Here’s a view from above the 80C31-con-
trolled power supply. The digital part is constructed
using point-to-point wiring. I used a ready-made PCB
for the analog part.
Figure 3—When looking at the analog portion of the power supply, you notice that the rectifier diodes convert alternating current to pulsating DC.
28
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
is compared to the voltage generated
by the DAC. The comparator U5
LM358 controls the series pass ele-
ment in order to regulate the current
output of the power supply. R11 and
R15 are a sampling element of the
output voltage. The two resistors form
a voltage divider and scale the voltage
by 10. Thus, a 23-V potential becomes
2.3 V. The comparator U5 LM358
compares this potential to the voltage
generated by the DAC and in addition
to controlling the series pass element,
which regulates the output voltage of
the power supply.
D15 and D16 isolate the two op-
amps. D8, D9, D10, and D11 protect
the analog switch and ADC when
there is an error and the sampled volt-
age or current rises above 5 V or drops
below zero. C10 and C11 serve as fil-
ter caps to smooth the sampled volt-
ages. R14 and R18 limit the current
from the sampling points. R28, R29,
D19, and D20 act as a regulator to
limit the voltage going to U7 MC4741.
If the circuit is unloaded, the B+
potential can reach as high as 31 V.
And if this reaches U7, it will suffer
electrical overstress, or EOS.
The firmware, which can be down-
loaded from the Circuit Cellar web
site, is written in assembly language
using a Metalink assembler. One
thing to note is why the reference is
2.55 V. The reason is that the ADC
and DAC values go from zero to 255.
Therefore, if you use 2.55 V you won’t
need to compute the values needed to
obtain a desirable voltage or the read-
ing obtained by the ADC. With this
scheme, you can simply read the ADC
and move the decimal point. For
example, a 100 reading from the ADC
is equivalent to a 10-V potential. And
with an 8-bit value, the resolution of
the voltage is 100 mV and the resolu-
tion of the current is 10 mA. To pro-
gram a 1-A current you can send 100
to the current DAC. To program 1 V,
simply send 10 to the voltage DAC.
CONSTRUCTION AND ASSEMBLY
You can construct the digital part of
the power supply by using point-to-
point wiring. I built a PCB for the ana-
log component, however, the one I
made was not that great because its
only purpose was to verify if the cir-
cuit works (see Photo 2). For the digi-
tal part, I used ordinary IC sockets and
wrapping wire to connect the circuit.
You should also use IC sockets so you
can remove the IC if it’s defective.
Before inserting the ICs, be sure to
look for the presence of 5 V at the V
CC
pins. Also, check if the ground pins
are indeed grounded. It’s a good idea
to use different colored wires so you
can trace the signals of different pins.
If you’re going to make a PCB for the
analog part, try to be sure the sampling
network is close to the output con-
nector or pads. Make the traces wide
for nets carrying power from pulsating
AC to DC. To calibrate the power
supply, burn the calibrate program into
to the 27C64 EPROM and then power
up the circuit. Adjust variable resistors
R2 and R3 until you read 2.55 V on
pins 1 and 7 of U9 LM358. Also, adjust
variable resistor R27 until you get a
reading of 2.55 V going to pin 12 of U4
ADC0820. Key in 5.0 for voltage and
adjust variable resistor R11 of the ana-
log portion until you get a 5-V reading.
TROUBLESHOOTING
The only way you’ll know if the
circuit is wired correctly is if you can
see messages coming out of the LCD
module. The program will work even
if the ADC or DACs are absent from
the circuit. However, this is not the
case with the LCD module. The pro-
gram will hang if the LCD module is
not present with dps.bin or dps.hex
loaded in the 27C64 EPROM. This is
because the BUSY pin of the LCD
module is polled to check if the LCD
is busy or not.
If the circuit doesn’t work, then
check for the presence of 5 V at the
V
CC
pins. You should also look to see
if the ground pins are connected to
ground, and if the reset circuit works.
Use a logic probe or an oscilloscope
to verify this. Additionally, always
make sure the crystal and pins X1 or
X2 of the microcontroller are in good
shape. If there’s no output on the
LCD, then reassess your wiring.
You should also watch for the
activity of enable E, RS, and R/W
pins. Adjust variable resistor R1 for
good contrast so you can see the char-
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
29
acters. If Enable E is not pulsating,
inspect the NAND gate (U10). Check
if the *RD and *WR signals are pul-
sating at the pins of the NAND gate.
Another good idea is to verify
whether or not the LCD is being
selected. To do this, probe pin 12 of
the U8 address decoder U8.
Key in 5.0 for voltage. If the read-
ing is zero, look to see if the VRDG
from the analog portion is connected
to the digital portion, which can be
confirmed by inspecting pin 12 of the
U7 CD4053. You should read 0.5 on
a multimeter.
You should always make sure that
you wired the U4 ADC0820 correctly.
Look for the *RD signal, *WR signal,
and chip select pulse at the pins of U4.
Key in 0.05 for current and connect a
4.7-
Ω
, 5-W resistor across the output
terminals. The reading for current
should be 0.05 A on the LCD. If it
isn’t, check for a 0.05-V reading on a
multimeter on pin 13 of the U7
CD4053. If that doesn’t work, check if
the IRDG signal from the analog part
is connected to the digital part.
The U7 MC4741 of the analog part
should be wired correctly and the IC
itself should be in good shape. If both
voltage and current readings are the
same, see if the SELECT signal at
pin 11 of U7 CD4053 of the digital
portion is pulsing. If during the cali-
bration phase there is not 2.55 V at
the U9 LM358, even if you adjust vari-
able resistors R2 and R3, then inspect
your DAC wiring.
Scan for the presence of *WR pulse
at the pins of the U5 and U6 AD7524.
In addition, you should check to see
if the chip select signals are pulsat-
ing at pin 12 of U5 and U6 of the
AD7524. If they aren’t, take a peek at
the 74HC138 address decoder U8.
And don’t forget to verify the condi-
tion of the LM358 U9. If you don’t
find 2.55 V at pin 12 of ADC0820 U4,
then make sure the LM336-2.5 D4 is
wired correctly. Finally, if you don’t
have –2.5 V at pin 15 of U5 and U6 of
the AD7524, check the wiring of
LM336-2.5 D14. If the programmed
voltage and current are not correct,
even if the voltage DAC and current
DAC have correct outputs, take a look
at the LM358 U5 of the analog part.
USING THE POWER SUPPLY
To achieve an output of 700 mV,
key in .7. For an output of 5 V, use
5.0. It will detect the number of
keystrokes needed by the position of
the decimal point. Therefore, to out-
put 10 mA you need to press 0.01 or
.01; and to output 500 mA, use 0.50
or .50. To output 1 A you’ll have to
key in 1.00, and so on. Remember to
press the Set Voltage button first in
order to set the voltage, and then
press the Set Current button to pro-
gram the current.
ADDITIONAL USES
The 80C31-controlled power supply
has many uses. You can power
numerous circuits on your work-
bench or charge a 6-V gel cell for con-
stant voltage charging and to limit
the peak current. In addition, you’ll
find that you can use the 80C31 to
charge your NiCd batteries by setting
the voltage higher than the battery
potential and the current to 50 mA.
I
SOURCE
80C31 Microcontroller
Intel Corp.
(602) 554-8080
www.intel.com
Noel A. Rios is an electronics and
communications engineer. He has
worked with semiconductor and elec-
tronics companies like Microcircuits,
IMI, Allegro, and ASTEC. His interests
include computers, embedded control,
power conversion, test and measure-
ment, and GPIB control. You may
reach him at nar@edsamail.com.ph.
RESOURCES
Intel Corp., Embedded
Microcontrollers 1986 DataBook
,
Intel, Mt. Prospect, IL, 1995.
Philips Semiconductor, Philips
80C51 Family Databook
, Philips,
Sunnyvale, CA, 1994.
SOFTWARE
To download the firmware, go to
ftp.circuitcellar.com/pub/Circuit_
Cellar/2002/144/.
30
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
n Part 1 of this
series, you learned
how the OSMC board
operates and became
acquainted with its advantages and
value. Now it’s time to discover how
the control signals are delivered to the
Open Source Motor Controller
(OSMC). The Modular OSMC Brain
(MOB) controls this process.
The MOB is a full-featured controller
for two OSMC power H-Bridge boards.
Figure 1 shows a block diagram of the
basic setup, which is designed to
achieve electronic speed control. The
MOB takes the signals from a standard
hobby radio control receiver and gener-
ates the proper control signals to drive
a pair of OSMC boards. The system is
flexible; it can directly control each
channel for two-stick operation or mix
two channels for single-
stick control. In addition,
it has a third auxiliary
channel that controls a
pair of optoisolators for
switching relays or other
devices. It supports 2-, 4-,
16-, and 32-kHz PWM
selection, an adjustable
dead band, I
2
C interface,
and serial interface. The
MOB has spare analog I/O
channels for expansion of current or
velocity sensing, for example. Locked
Antiphase and Sign Magnitude PWM
are supported as well. The user inter-
face is primarily through a 4 × 20 LCD
display and four command buttons.
Are you excited yet?
THE “BRAINS”
At the core of the controller is the
powerful Atmel AVR ATmega163, a
high-performance 8-bit RISC processor
running at 8 MHz. [1] The RISC archi-
tecture of the Mega163 allows it to
achieve nearly 8 MIPS of processing
speed while consuming little power.
The Mega163 includes 16 KB of flash
memory, 1 KB of RAM, and 512 bytes
of EEPROM. In addition, it’s pro-
grammed in GNU C for the AVR and
uses AvrX, Larry Barello’s RTOS.
One of the most attractive features
of the Mega163 is that it can be pro-
grammed in-circuit using simple, low-
cost hardware. In-circuit programming
allows you to upload software updates
such as new features, enhancements,
or bug fixes after the MOB circuit
board has been completed (i.e., popu-
lated and soldered).
To achieve this handy feature, the
MOB comes with a standard 10-pin 2 ×
5 header connector for programming
the Mega163. The header is located
near the LCD connector on the board.
The format of this header matches the
STK200/STK300 standard supported
by most programmers and software
that sustain the ATMega family.
One of the most popular and best
supported of these programmers is
PonyProg, which was written by
Claudio Lanconelli (Circuit Cellar 142).
The OSMC group recommends this
Mega163 programmer because you can
download the user-friendly software
Extreme OSMC
i
Last month, Sonny
taught you how the
OSMC board func-
tions. Now he’s going
to show you an inex-
pensive way to
assemble and use a
Modular OSMC Brain,
which is a controller
that uses the signals
from a radio control
receiver to drive
OSMC boards.
Sonny Lloyd
ROBOTICS
CORNER
MOB
RC
Serial
SPI
I
2
C
PWM
PWM
AUX Out
OSMC 1
OSMC 2
Motor
Motor
Switch
Figure 1—First, check out a conceptual diagram of the OSMC project.
Part 2: The Modular OSMC Brain
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
31
the auxiliary signal to control a weapon
for my fighting robot. Connecting
only AUX 1 provided an ability to
control a single weapon. To turn on
the weapon, the control stick (or
switch) is set to a value above the cen-
ter point. To turn it off, the stick is
centered or moved below the center
point. And if you want to control a
bidirectional weapon, such as an arm
that extends and retracts, then one
AUX output is used for extension and
the other for retraction. Because the
AUX outputs are never both on at the
same time, the weapon will respond
as expected to all command inputs.
MANY, MANY FEATURES
If you wish to customize the exact
operation of the MOB, you’re in luck!
The MOB software provides several
user-configurable parameters to opti-
mize its operation for a particular robot
and usage scenario. The MOB’s soft-
ware user interface consists of seven
screens on a 4 × 20 LCD and four push
buttons, which allow you to change
the screens and make selections.
One option is to set the PWM fre-
quency to 2 (default), 4, 16, or 32 kHz.
In some applications, it may be neces-
sary to have fast signal refresh rates,
however, the 2-kHz default will suffice
for combat robot operation. Two of the
most common PWM techniques are
also selectable: Sign Magnitude and
Locked Antiphase modes. These two
modes determine how the legs
of the H-Bridge are pulsed.
The sign magnitude PWM
control scheme requires the
use of two I/O lines. One data
line carries the sign bit—
which is sometimes referred
to as the direction bit—and
for free and the hardware is easy to
build. And I’m sure this goes without
saying, but all software revisions to be
uploaded to the MOB are freely avail-
able from the OSMC project web site.
CONTROLLING THE MOB
The MOB circuit board in Photo 1
may look like a simple design, but
don’t be fooled. The MOB is a complex
programmable device, but it’s designed
to be flexible and useful for a large
number of applications. It receives
information through three radio servo
inputs. The Mega163’s software con-
verts the 2-ms servo pulses, using the
pulse position modulation (PPM) tech-
nique, into three separate pulse width
modulated signals. The first controls
the throttle; the second controls the
direction; and the last signal—the aux-
iliary—essentially serves as an on/off
switch for some external device. In
order to make the MOB more adaptable
to different styles of user interface (e.g.,
joysticks), there are two different selec-
table control methods: Normal mode
and Mix mode (see Table 1).
If you prefer to rely on your intuition
and a single joystick to control your RC
project’s speed and direction, then Mix
mode is for you. As you might suspect,
when the stick is pushed forward the
MOB propagates a signal such that
both motors move forward proportion-
ally. The same is true when pulling
back on the joystick, except that the
motors now move in reverse.
Therefore, the throttle input
controls the speed of both
motors equally. To turn right
or left, one motor’s speed
must be decreased while the
other’s is increased. And so,
while in Mix mode, the direc-
tion input signal causes a differential
to be added or subtracted from the
throttle speed setting for each motor.
Mix mode is generally the best
choice for high-speed driving. But if
you want to maneuver your project as
if it’s a tank, then Normal mode is for
you. Using two joysticks to independ-
ently control the speed of each
motor’s forward or reverse motion is
tricky, but sometimes it’s preferable.
For instance, if the left joystick is
pushed forward while the right joy-
stick is pulled back, your robot would
spin on a dime in a clockwise rota-
tion. Normal mode should be selected
for slower operation or sharp turns; it
should also be selected if the trans-
mitter you’re using contains its own
channel-mixing scheme. The latter
allows the use of any off-the-shelf
transmitter/receiver combination as
an input to the MOB.
The auxiliary signal is controlled in
the same manner in either Mix mode
or Normal mode. The auxiliary output
is split into two signals, AUX 1 and
AUX 2. The AUX 1 and AUX 2 out-
puts are optically isolated from the
rest of the MOB circuit, and are
designed to safely activate relays or
other high-power devices without the
risk of electrical feedback affecting the
MOB. They work in a complementary
fashion such that when AUX 1 is on,
AUX 2 is off (and vice versa).
The operation of the two outputs is
as follows: If the RC signal connected
to the auxiliary input is above the
center value output, then AUX 1 will
be turned on and AUX 2 will be
turned off; conversely, when the signal
is below the center value, AUX 2 will
be on and AUX 1 will be off. There is
a large enough deadband so that both
AUX 1 and AUX 2 remain off while
the stick is in the center position.
This creates a number of options for
controlling on/off devices with the
auxiliary channel. In my case, I used
Photo 1—The modular OSMC brain provides the sig-
nal processing for the electronic speed controller.
Table 1—You can control the MOB in Mix or Normal mode. The former works
best for one-stick operation and the latter works best for two-stick operation.
Name
Mix mode function
Normal mode function
Throttle
Speed forward or reverse
Motor A speed
Direction Steering right or left
Motor B speed
Auxiliary Switch AUX 1 and 2 outputs on or off
Photo 2—The µMOB is an excellent alternative for
people who desire a simple-to-operate yet powerful
motor driver.
32
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
high-side leg of the
OSMC and the oppo-
site low-side leg
together so they can
be driven on or off
simultaneously. The
same is true for the
other two legs of the
H-Bridge. The locked
antiphase method is
demonstrated in
Figure 3, where the
red and blue lines rep-
resent current flow
corresponding to their
respective color-coded control signal.
When the joystick is in the center
position, the PWM duty cycle is 50%.
Both locked pairs of legs receive the
same amount of on time in a given
period, so the average voltage across
the motor is effectively zero. To change
the direction motor rotation to forward,
simply increase the duty cycle above
50%; to reverse direction, decrease the
duty cycle below 50%. The overall
control of the motor’s speed is accom-
plished by calculating how much the
duty cycle has changed. For instance,
a 90% duty cycle would cause a for-
ward motion of the motor at a fast
pace (though not quite at full speed). A
45% duty cycle, however, would cause
a slow-moving reverse motion because
it deviates from 50% by a mere 5%
and because the cycle is less than 50%.
Another highlight of the locked anti-
phase scheme is the ability to receive
regenerative braking for free because
there is always one pair of locked legs
to provide a conductive path back to
the batteries. Recall that when a motor
will hold one side of the H-Bridge
(OSMC) in an on state. The second
I/O line carries the magnitude signal.
The duty cycle of the magnitude
PWM signal causes an average load
voltage to appear across the motor ter-
minals. This PWM signal is applied to
the opposite leg of the sign bit, as
indicated in Figure 2.
Pulsing the H-Bridge by means of the
sign magnitude method has the distinct
advantage of being easy to implement,
and thus it’s the default setting. There
are, however, some disadvantages. One
negative aspect of the sign magnitude
PWM control scheme is recognized
when the motor is freewheeling or
coasting. During this action, the stored
current in the motor travels through
the top two high-side MOSFETs and
back, effectively wasting energy in the
form of heat. Another disadvantage is
that this mode uses up two I/O lines
of the microprocessor in an environ-
ment that is already low on spares.
The other method of control, locked
antiphase PWM, was implemented
solely for experimentation.
The results proved that
operation in this scheme
requires a high frequency,
which is not suitable for
the OSMC. However,
because of the expanding
nature of the OSMC proj-
ect, it may one day become
a practical option. One rea-
son to look into this
scheme is its ability to con-
trol the H-Bridge using only
one signal line. The locked
antiphase PWM method
achieves this by locking one
brakes, it’s essentially acting as a gener-
ator, which, in fact, recharges your bat-
teries (if only slightly). One noticeable
problem, however, is that it’s difficult
to tune all the settings of the MOB for
optimized locked antiphase operation.
If you’re still not satisfied with the
joystick interface, the MOB has yet
another feature that will help to
improve this: a selectable dead band
value of zero to eight, where an eight
represents approximately a 10% stick
throw dead band. A deadband of two
is the default setting.
Do you want more features? The
MOB can monitor the battery supply
to each OSMC board with auto shut-
down for droop protection. And, as if
all of this were not enough, you’ll find
it convenient that the on-board EEP-
ROM can store all of your settings and
automatically load them into the
MEGA163 at start-up or reset.
THE µMOB
The Micro Modular OSMC Brain
(µMOB) was created by Larry Barello
to suit the needs of people who
require a fully functional, reliable,
high-quality motor controller without
all of the bells and whistles of the
MOB (see Table 2). You can assemble
this package on your own by following
the detailed assembly instructions
found on the OSMC project’s web site
(see Photo 2). The µMOB can be used
to drive any motor controller (e.g.,
OSMC) that accepts PWM, DIREC-
TION, and ENABLE signals.
FUTURE CONSIDERATIONS
There are many options, add-ons,
and features that I would
love to see included in
the MOB in the future.
There are four general-
purpose unused analog
inputs that could be easi-
ly adapted to help facili-
tate this. Currently, one
add-on package that is
being explored is some
sort of system feedback,
which would be highly
valuable because it would
allow for straighter steer-
ing and improved control
at high speeds.
Motor
5V
8V
5V
8V
5V
8V
5V
8V
Battery
Figure 2—With the sign magnitude PWM control scheme, one leg is held on
while the opposite leg has the PWM applied to it.
Figure 3—The PWM signal is applied to all four quadrants in Locked Antiphase mode.
Motor
5V
8V
5V
8V
5V
8V
Battery
5V
8V
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
33
BUILD IT YOURSELF
What else can I say? Everyone on the
OSMC design team is pleased with the
outcome of the project. The approxi-
mate cost of the entire electronic
speed controller was kept within rea-
son. The OSMC board’s components
cost about $100, and the MOB can be
assembled for approximately $35.
That’s a great deal given the OSMC
project’s capabilities and reliability.
I hope you enjoy building this elec-
tronic speed controller as much as I
did, and that you’ll join us in dis-
cussing related topics (or not) on the
official web site’s message board.
I
REFERENCES
[1] Atmel Corp., “8-bit AVR
Microcontroller with 16K Bytes
In-System Programmable Flash—
Atmega163, Atmega163L,” rev.
1142c, September 2001.
Sonny Lloyd graduated with a BS in
Electrical Engineering from Ryerson
University in Canada. While attend-
ing university, he worked a 16-month
internship at Siemens Westinghouse
Power. He hopes to win top rankings
next year with his OSMC project in
local and international robotics com-
petitions.
Table 2—As you’d suspect, the technical specifications of the µMOB are closely related to the MOB.
Technical Specifications
R/C input range
100 10-µs steps between 1 and 2 ms
Sign magnitude PWM output
±32 steps at 10 µs per step (~3 kHz)
Dead-band
Selectable 40 or 80 µs
Input mixing
Selectable mixed (single stick) or normal (tank style)
Brake mode
Selectable brake/coast
Outputs
10-pin headers compatible with the OSMC H-Bridge board
Auxiliary outputs
Two open-collector terminals suitable for driving relays
Supply voltage range
6.5 to 15 V (LM2940)
BEC output
5-V, 0.7-A maximum (limited by the 12-V supply)
RESOURCES
µMOB Circuit board, starter kits
Larry Barello
e-mail: larry@barello.net
SOURCES
Atmel AVR Atmega163
Atmel Corp.
(408) 441-0311
www.atmel.com
OSMC, MOB, µMOB board
Chris Baron and Dennis Millard
www.robot-power.com
PonyProg
Claudio Lanconelli
www.lancos.com/prog.html
SOFTWARE
To download the code, go to
ftp.circuitcellar.com/pub/Circuit_
Cellar/2002/144/.
34
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
ack in May, I
described the chal-
lenges high intensity
radiated fields (HIRF)
present to your designs (“Working With
EMC,” Circuit Cellar 142). You learned
that radiated fields were composed of
electric (E) and magnetic (H) compo-
nents, and that their ratio, or wave
impedance, for predominantly electric
fields becomes a constant 377
Ω
. You
should remember this number because
many RF engineering concepts rely on
it. For example, the commonly used
200-Vpm e-field immunity requirement
originated from the assumption that RF
power at 100 W per square meter is
dangerous to humans:
Hence, the magical 200-Vpm e-field
immunity requirement for electronic
equipment in vehicles.
Transients such as a lightning strike
and electrostatic discharge (ESD) pres-
ent a different set of problems. You
must remember that transient protec-
tion will not work without good EMI
immunity. Therefore, transient limiters
are usually physically located before
EMI filters. There are two reasons for
this, and if you consider the circuit
topology and cabinet construction in
Figure 1, you’ll see why this is the case.
V
= P
×
R
= 100
×
377= 194.16
First, most low-pass filters can han-
dle only limited voltage (usually 50 V),
which means they’re likely to get
destroyed by larger transients. Second,
every transient protection device oper-
ates at a finite speed. Consequently,
the clamp always leaves a residual
pulse that must be filtered out before
it enters sensitive circuits and causes
damage. This is especially true of
electrostatic discharge.
The need to place transient limiters
before the low-pass filters also
explains the difficulty with making a
sealed box, as well as the need to use
the dual cavity design for e-fields in
excess of 100 V per meter when
immunity to large transients is also
the design goal. [1]
Obviously, designers in the automo-
tive, aerospace, and communications
industries have to worry about the
possibility of lighting strikes. But
even the humblest consumer appli-
ances can be exposed to unexpected
transients. Therefore, many consumer
products can benefit from some level
of transient protection.
All modern designs that use thin
film components and microelectronics
must address ESD, which is an espe-
cially sneaky threat because it can
weaken a microelectronic device or
cause latent damage. In cases in which
ESD damage occurs, failures often arise
at the worst possible moment. Some
ICs are advertised as containing inter-
nal ESD or transient protection, which
is better than nothing. But you should-
n’t rely on them exclusively except for
the most rudimentary designs.
DAMAGE TOLERANCE
Two major problems can arise when
a system is exposed to transients.
First, the equipment can be badly
damaged or destroyed completely. You
can prevent this by clamping or oth-
erwise limiting the transients. The
second problem the system can expe-
rience is a functional upset, which
can occur even when the transient is
well clipped and no damage to the
equipment is apparent. Because dam-
age prevention is prerequisite, we’ll
first consider ways to ensure damage
tolerance before tackling the problem
of functional upset.
Taming the Transients
b
Transients, such as
electrostatic dis-
charge and lightning,
can create major
problems for many of
your electronic
designs. However,
there are several
ways to limit the com-
ponent damage and
functional upset that
results from transient
exposure.
George Novacek
FEATURE
ARTICLE
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
35
mathematically defined by the fol-
lowing equation:
This equation is also known as
Thevenin generator. Here, V
0
is the
peak voltage and f the frequency.
What kind of clamps can you use
for transient protection? Here are the
characteristics of an ideal clamp: a
low, precisely defined clamping volt-
age; immediate response; unlimited
energy absorption; no follow-on cur-
rent; no leakage; and it would be
small, light, and inexpensive. In real
life, however, we must compromise.
Metal oxide varistors (MOVs) or zinc
oxide varistors are used in commercial
and industrial applications. Their V/I
characteristics are nonlinear and look
similar to two back-to-back Zener
diodes with symmetrical bipolar clamp-
ing. Because their standby resistance
is in megaohms, they have a fairly low
leakage, no follow-on current, and a fast
response time. But despite the fact that
they’re small, light, and inexpensive,
these clamps are used reluctantly. It’s
been said that they tend to deteriorate
with age and use, but I haven’t seen
data proving appreciable deterioration.
Unfortunately, the effectiveness of
transient suppressors can’t be moni-
tored on an ongoing basis, so you have
to rely on previous experience. And
it’s usually too late by the time you
discover that the device has failed. In
this respect, a varistor’s Failure mode
is short circuit, which is the preferred
failure in terms of damage tolerance.
A similar clamping effect could be
achieved with Zener diodes, but
their energy handling capability is
poor with respect to their size and
cost. Instead, transzorbs have
become the popular clamp for crit-
ical applications. Transzorbs,
which are avalanche-type semicon-
ductor devices, are a trademark of
General Semiconductors.
Transzorbs that are similar in
size to 0.5-W Zener diodes are fast,
have low capacitance, and can han-
dle large peak pulse currents. They
come as unipolar and bipolar in sin-
gle and multiple packages that don’t
appear to deteriorate with use.
V (
t) =1.033 V
0
×
sin 2
π ×
f
×
t
×
e
π ×
f
×
t
24
–
As with EMI protection, good
grounding and bonding are essential.
Grounding and bonding practices
deserve a separate article for a full
explanation, but for now I’ll just clarify
the terms. Grounding is the process of
connecting a conductive medium to a
reference point (e.g., a PCB ground
plane or equipment enclosure).
Remember, be careful and make sure
you don’t create ground loops. Electrical
bonding is the joining of two or more
conductive surfaces to obtain an elec-
trically conductive, low-resistance 1-
to 3-m
Ω
path. Because this path serves
to divert high energy (often with high
frequency content), it’s important that
its inductive component is extremely
low as well. Poor bonding can easily
turn into a good antenna, defeating
the entire EMC scheme.
PIN INJECTION
The effectiveness of the transient
protection scheme is tested by pin
injection. Figure 1 shows a two-stage
protection circuit that will work for
the most demanding applications.
Depending on the actual require-
ments, this circuit can be modi-
fied. To pass the test, a transient
generator is, in turn, linked to
every connector pin and then
10 transients of each polarity are
applied. To make it more difficult,
the equipment is usually not pow-
ered during the test. After every
connector pin has been exposed,
the unit is then powered up and
its functionality is assessed.
In order to select the compo-
nents shown in Figure 1, you must
understand the type of transients
you’ll need to clamp. Refer to Figure 2
to see what it’s like when lightning
strikes an aircraft. This beauty reaches
220,000 A! Fortunately, electronic
equipment is rarely subjected to a
direct hit, so the actual exposure is
significantly lower. But notice that it’s
all done and over with in about 0.1 ms.
Unlike HIRF, transients are better
described in time, as opposed to fre-
quency domain. You can see that the
fast rise time will result in a broad fre-
quency spectrum and that there’s not
a clamp fast enough not to allow a sig-
nificant spike to go through into the
following circuits.
The depiction in Figure 2 is a com-
mon double exponential transient
pulse waveform. It’s defined as:
Here, a variety of differing peak cur-
rent values I
0
and time constants a
and b are used to simulate induced
transients. Figure 3 is the burst of a
1-MHz decaying sine wave that’s
I (t) = I
0
(
e
at
e
bt
)
–
t
0
0
1 × 10
–4
2 × 10
–4
3 × 10
–4
4 × 10
–4
5 × 10
–4
6 × 10
–4
2 × 10
5
1.8 × 10
5
1.6 × 10
5
1.4 × 10
5
1.2 × 10
5
1 × 10
5
8 × 10
4
6 × 10
4
4 × 10
4
2 × 10
4
I(t)
Figure 2—A double exponential transient waveform like this one
can be seen after a lightning strike. This one reaches its 220-kA
peak value in 6.4 µs, decaying down to 110 kA in about 70 µs.
For level 4 pin injection, the same timing is used with 750-V open
voltage and 150-A or 750-A short circuit current.
Figure 1—The I/O circuit has dual-stage transient protection and EMI filters. Dual spark gaps are ideal for sym-
metrical circuits because both clamps fire at once.
wound or carbon film (I don’t know if
anyone still manufactures the carbon
film). Regardless of the current, most
modern resistors will not survive
750 V or more across their terminals.
If you can, you should follow the
transzorb with an RC low-pass filter
to absorb the remnant spike. For dis-
crete inputs, this could also function
as a debouncing filter. Anything from
10 to 60 ms should be fine. Your soft-
ware can handle the main portion of
debouncing, but the 10-ms delay will
clean up the signal and help with EMI.
Power lines, communication lines,
and output drivers can’t afford to have
it, so keep an eye on the remnant
transients.
Whether or not you’ll need the low-
pass pi filters F1 and F2 in addition to
the dual cavity packaging will depend
on your HIRF immunity require-
ments. If you don’t need them, it
would be a good idea to use ferrite
beads or another form of low-pass fil-
ter with a critical frequency above
1 MHz. The remnant transients, espe-
cially those from electrostatic dis-
charge, are extremely narrow and RC
filters may not be efficient in sup-
pressing them because of their para-
sitic impedances.
Finally, let’s talk about the reverse
biased diodes D3, through D6. These
diodes ensure that the IC pins don’t
move more than one diode drop out-
side the power supply range. Although
many ICs have internally protected
pins with the same diode arrange-
ment, you still need to be care-
ful. The internal diodes may be
capable of absorbing the rem-
nant spike, but there are other
issues to address as well.
Surge protectors have finite
internal impedance. A 5-V
logic circuit needs a clamp that
presents negligible leakage at
5 V, so it would have the
breakdown voltage at around
5.2 V. But during the transient,
the voltage across the clamp
could easily rise above 6 V.
That wouldn’t be healthy for
the IC. The situation becomes
more serious when the tran-
sient arrives and the unit is
not powered. In the absence of
36
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
When a large amount of energy
requires clamping, a Zener diode/SCR
combination is often used. When the
breakdown voltage of the Zener diode
is exceeded, the SCR fires and crow-
bars the protected line. This is essen-
tially a short circuit, and it’s often
used to blow a much slower protec-
tion fuse. One disadvantage of the cir-
cuit is the follow-on current, which
must be interrupted for the SCR to
open up.
Spark gaps, or gas discharge tubes,
are capable of conducting high cur-
rents (see Photo 1). Their response
time is fairly slow and minimum igni-
tion voltage is above 100 V. After
they’re fired, there’s follow-on current
flowing with a voltage drop of about
20 V across the gap until the current
has been interrupted externally.
Because of these characteristics, spark
gaps are primarily found in two-stage
protection circuits (see Figure 1) or
schemes protecting high-voltage lines.
A dual spark gap has a center elec-
trode shaped like a ring. When
one line fires as a result of over
voltage, the other line ignites as
well. This is useful for protec-
tion of symmetrical circuits.
PRACTICAL DESIGN
APPROACH
Referring back to Figure 1,
you can see that the threat level
and maximum value of resistors
R1 and R2 will determine
whether or not the spark gap is
needed in the first stage. The
test waveforms are defined in
terms of the generator’s open
voltage and short circuit cur-
rent. As long as R1 and R2,
which limit the maximum pulse
current in the clamps,
can be at least 20
Ω
, you
can usually select small
size transzorbs. They are
reliable enough to handle
Level 4 lightning (the
highest level is 5) as it is
defined for avionic equip-
ment. This consists of the
750 V/150 A or 750 V/
750 A test pulses (see
Figure 2). The 1500 V/60 A
burst is depicted in
Figure 3. Level 4 protection is well
beyond the requirements of any com-
mercial product yet is easy and inex-
pensive to achieve.
If you can’t insert an inline 20-
Ω
resistor, which may be the case with
power or output driver lines, the fast
rise time of the transient should allow
you to replace it with a choke to limit
the current pulse. If that’s not possible
because of bandwidth limitations,
you’ll have to use a higher energy
rated device (e.g., a transzorb or varis-
tor) or a spark gap.
I prefer to go to the second stage by
using the spark gap to cut the initial
pulse down around 100 to 200 V, and
then follow it with a small transzorb.
For the majority of signal lines, R1/R2
can be hundreds of ohms. This allows
the transzorbs to operate well below
their rated power. Read the
“Calculating Transient Protector
Rating” sidebar to learn how to calcu-
late the transient protector rating.
Make sure the R1/R2 resistor is wire
10,000
1000
100
10
1
0.1
0.01
0.001
10
2
10
3
10
4
10
5
10
6
10
7
10
8
F
(H )
Surface transfer impedance IZTI m
Ω/
m
Aluminum/Mylar foil
Solid
copper
screen
Double
braid
Single braid
Optimized
single
braid
Triax
braid
Figure 4—This plot of transfer impedance shows several common cables.
Figure 3—A decaying sine wave is another pin injection waveform. For
level 4, it’s a 1500-V per 60-A burst of 1 to 10 MHz, depending on the
system resonance.
V t
( )
0
–2000
–1000
0
1000
2000
5 × 10
–6
1 ×10
–5
1.5 × 10
–5
2 × 10
–5
2.5 × 10
–5
3 × 10
–5
3.5 × 10
–5
4 × 10
–5
Time
the internal power, the junctions have
no reverse bias and the 5- to 6-V pulse
would feed directly through the IC
into a short circuit presented by the
power supply and its bypass capaci-
tors. If the IC internal protection
diodes can handle the full brunt of it,
then your design should be fine. But
make sure!
FUNCTIONAL UPSET
Knowing that your design survived
a lightning strike is only one part of
the story. What will the system do
when the strike is over? A scrambled
television picture or a crackling
sound in the telephone would be
understandable, but the in-flight
flame out of a turbofan engine could
be catastrophic.
Transients, especially those caused
by lightning strikes, can couple
through the magnetic field into the
system wiring and cause common
mode interference. To examine your
system’s behavior, inject test wave-
forms that are similar to those in
Figures 2 and 3 through a current
transformer into the wire harness. [2]
Will the cable shielding help?
At frequencies below 100 kHz, non-
magnetic (standard braid) copper or
aluminum wire shielding has little
effect in a magnetic (H) field, because
the skin depth of these materials is
high. [1] Above 100 kHz, the skin
depth is sufficient enough to begin to
absorb some of the H-field. This cre-
ates voltage and current in the shield
ground loop. As the shield-to-ground
bond impedance increases, the voltage
coupled in the inner wire decreases.
This occurs because the coupled volt-
age is a function of the shield current.
Ultimately, the least amount of cou-
pling is achieved by disconnecting one
end of the shield from ground, which
is contrary to the best e-field shielding
requirements. It may be a good com-
promise if the equipment is intended
to work primarily in low-frequency
interference environments.
The concept of shield transfer
impedance was developed to address
the coupling of a magnetic field into a
shielded wire. It is expressed as:
where V is the voltage induced in the
inner wire and I
S
the current induced
in the shield. Figure 4 shows the plot
of transfer impedance for several
types of cable. For example, let’s
assume you use a 10
′
(3 m) long dou-
ble-braided cable to interface your
electronic controller. Here, Z
T
would
be around 5 m
Ω
per meter in the fre-
quency spectrum of 1 to 10 MHz,
where the lightning transients are
often found. When the 750-V/750-A
transient shown in Figure 2 is inject-
ed into the cable through a current
transformer the result is:
This pulse would be safely clamped
(as shown by the previous pin injec-
tion test). Because it would last
around 100 µs, the resulting distur-
V = Z
T
×
I
S
×
l = 5
×
10
–3
×
750
×
3 = 11.25
V
Z = V
I
× Ω
m
T
S
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CIRCUIT CELLAR
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Issue 144 July 2002
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38
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
bance could be filtered out so that the
system couldn’t even hiccup.
Unfortunately, this is not always
the case. When the surge protectors
begin to clamp, the signal that’s super-
imposed on the transient also starts to
clamp. On the differential lines, the
transient may look like a bona fide
signal (i.e., a trigger pulse), but on
common mode lines both lines may
swing to the point where signals are
obliterated. A DC offset could also
appear on differential and/or common
mode lines because of the rectifying
action of the surge protector followed
by low-pass filters. Either way it’s a
problem. The simplest solution arises
when the system is allowed to shut
down and reset as soon as it detects
an invalid input.
How can you detect an invalid
input? It’s the voltage resulting from
the clamping action of the surge pro-
tector, which the normal signal is not
allowed to reach. For example, a dis-
crete input could be 0 to 3 V as
logic 0 (you always want a nice noise
margin to avoid ground noise prob-
lems), or 3 to 5 V as logic 1. A clamp-
ing action would result in a voltage at
least one diode drop above 5 V or
below zero.
If you are not allowed to reset, then
the common approach is to hold the
last valid input for a predetermined
period of time. Two seconds is general-
ly considered the right amount of time
for the effects of a lightning strike to
settle down. If by then the input has
not gone back to the valid range,
there’s probably a failure. In this case,
another action, such as switching to a
backup channel, must be taken.
If reset or hold isn’t permitted, then
you’ll need to use symmetrical inter-
faces to ensure only common mode
swings of the signal lines. After that,
increase the common mode range of
close enough for you to select the surge protector. The
waveform can be divided into simple segments, and their
respective energies can be calculated and then added for the
total energy requirement. K = 0.637 for a half sine wave,
otherwise defined as:
K = 0.5 for the approximation of the rising part of the wave-
form in Figure 2,
K = 1.4 for the approximation of the falling part of the wave-
form in Figure 2:
Here,
τ
is the duration for I
pk
to drop to 50%. K = 0.86 for
the approximation of the damped sinusoid in Figure 3:
where
τ
is the duration for I
pk
to drop to 50%.
As an example, let’s take the pulse waveform in Figure 2
and split it into two parts (see Figure S1). The first section is
from zero until I
pk
reaches its maximum of 29.79 A, which
is the peak current calculated above. The time
τ
= 6.4 µs
and K = 0.5. For the decaying section,
τ
= 70 – 6.4 µs. The
clamping voltage is 5.2 V.
This amount of energy (14.25 mJ) is not high and there
are many devices in catalogs that will satisfy this require-
ment. Consult the manufacturers listed at the end of this
article in the Resources section. Their data sheets and
application notes
available at their
web sites contain
a wealth of infor-
mation.
I
pk
×
sin
π × ×
e
t
τ
–
t
I
p
k
×
e
1.44
× τ
t
I
pk
×
t
τ
I
pk
×
sin
π ×
τ
t
CALCULATING TRANSIENT PROTECTOR RATING
In order to select an appropriate surge protector, you
need to know how much energy it will have to dissipate.
Some manufacturers specify their device’s maximum cur-
rent and the timing of the pulse, but you can use Ohm’s
law to determine this on your own.
Let’s say the pulses of the shape but different timing
than shown in Figure 2 (6.4-µs rise time and 70-µs length)
are to be applied through a 750-V/150-A generator. Right
away this tells you that its source resistance is:
The current limiting resistance (R1 in Figure 1) is 20
Ω
and
the transzorb clamps is at 5.2 V, assuming the voltage is
constant and the internal resistance is negligible.
Therefore, the peak current the transzorb will be exposed
to is:
Now we need to find a device rated for 30 A and at least
7 A per 70-µs pulse.
Sometimes surge protectors are specified by the energy
they dissipate in joules (J). Looking at the waveform in
Figure 2, the energy is equivalent to the area surrounded
by the curve and can be calculated as
Here, V
c
is the clamp voltage, I is the peak current,
τ
is
the pulse duration, and K is a constant. Solving the inte-
gral based on the accurate waveform is laborious, so in
order to make your life easier, the constant K has been
published for differ-
ent shapes. It may
vary slightly with
respect to time con-
stants, but it’s
E =
V
C
( )
×
I(t)dt = K
×
V
C
×
I
× τ
0
t
t
I
P
= 750 – 5.2
5 + 20
= 29.79
A
750
150
= 5
Section 1:
E = 0.5 × V
c
× I ×
τ
= 0.5 × 5.2 × 29.7 × 6.4 × 10
–6
= 494 × 10
–6
J
Section 2:
E = 1.4 × V
c
× I ×
τ
= 1.4 × 5.2 × 29.7 × (70 – 6.4) × 10
–6
= 13.75 × 10
–3
Total = 14.25 × 10
–3
J
Figure S1—If you split the pulse waveforms shown in Figure 2, you get these two equations.
REFERENCES
[1] Oren Hartal, Electromagnetic
Compatibility By Design
, R&B
Enterprises, West
Conshohocken, PA, 1996.
[2] Texas Instruments, Inc., “ESD
Application Report,”
www.ti.com.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
39
transformers while eliminating
ground loops as well. DC inter-
faces would take a little more
effort, but the linear optocouplers
and isolation operational ampli-
fiers plentiful on the market can
solve most of your problems.
PARTING WORDS
The science of protecting your
equipment from transients isn’t
black magic. It just takes some
common sense and experience.
And the only way you’ll gain the
experience needed is by doing the
work; so don’t hesitate to plunge
right into it. Your designs will
benefit and you’ll learn a great deal.
I
RESOURCES
AVX Corp.
(843) 448-9411
www.avxcorp.com
CP Clare
(800) 272-5273
www.cpclare.com
General Semiconductors, Inc.
(631) 847-3000
www.gensemi.com
RTCA, Inc. “DO-160D
Environmental Conditions and Test
Procedures for Airborn Equipment,”
www.rtca.org.
Semtech Corp.
(805) 498-2111
www.semtech.com
your design so that the surge protec-
tors don’t fire as a result of the
planned environment. If you know
that the maximum planned transient
will cause an 11.25-V swing of the
lines, use 20-V surge protectors and
make sure the input has a 20-V com-
mon mode input range.
You can increase the common mode
input range with optocouplers and
George Novacek has 30 years of experi-
ence in circuit design and embedded
controllers. He is currently the vice presi-
dent and general manager of Hispano-
Suiza Canada, a division of Snecma, a
world leader in aerospace engine and
landing gear systems. You may reach
him at gnovacek@nexicom.net.
Photo 1—This is a dirty cavity with dual spark gaps and
transzorbs. This will guarantee survival in the worst lightning
strike environment.
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42
Issue 144 July 2002
CIRCUIT CELLAR
®
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like Microchip’s
PIC controllers
because they can be
used for many different
kinds of projects. There are, however,
instances when I would like to display
information from the PIC on panels
other than LEDs or seven-segment
displays. For that reason, I started
thinking about LCD panels.
LCD panels come in many different
varieties. You can choose from STN
and TFT, color and monochrome, 4- to
18-bit color depths, and various panel
sizes. However, it’s difficult to use an
LCD panel with the PIC because it
involves so many control signals. So,
this is where the Epson S1D13708
LCD controller comes into the picture.
The S1D13708 simplifies the inter-
face to the LCD panel to a single-chip
solution. The S1D13708 drives the
panel and adds various display fea-
tures like picture-in-picture and over-
lays. In addition, it boasts 80 KB of
static RAM that can be used for dis-
play purposes and to store data from
the PIC. For example, an Epson ND-
TFD 160 × 160 panel in 8-bit Color
mode uses 25 KB of RAM and leaves
55 KB for the PIC to store data.
Another advantage is that the
S1D13708 can interface directly to a
variety of native CPU buses without
glue logic. The one I’ll describe here is
the Indirect Mode 68 interface, which
is a 6800-bus interface with only one
address (A0) in use. The Indirect Mode
interface uses commands and data bus
cycles to access the internal compo-
nents of the S1D13708, so there is a
speed penalty for accesses. The
Indirect Mode interface supports
either an 8- or 16-bit wide data bus.
To reduce the number of signals need-
ed to implement Indirect Mode 68,
eight bits should be chosen.
Additionally, the interface requires
four more lines to act as control sig-
nals, which means a total of 12 lines
would be needed on the PIC. Using up
12 I/O lines may seem a bit overboard,
but the gain from adding the
S1D13708 definitely outweighs the
loss of the I/O lines.
In addition to the extra RAM, the
S1D13708 has seven I/O lines, eight
output lines, and a pulse width modu-
lated line. Because the interface bus
relies on *CS, the 11 PIC I/O lines are
free to be used for other purposes when
the S1D13708 is not being accessed.
HARDWARE CONNECTIONS
Connecting between the S1D13708
and a PIC microcontroller doesn’t
require external logic if there are
enough I/O lines and the voltage lev-
els of the two chips are the same.
LCD Controller for a PIC
i
Peter uses PIC parts
in many of his proj-
ects, but there are
times when he would
prefer to be able to
display PIC info on an
LCD panel rather than
on segment displays
or LEDs. In this proj-
ect, he shows us a
simple way to build an
LCD controller for a
PIC using few parts.
Peter Chia
FEATURE
ARTICLE
Photo 1—Here’s the PIC controller interfaced to the
S1D13708’s evaluation board.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
43
S1D13708. The pixel clock for the LCD
panel can be set as a derivative of the
main clock source using the S1D13708’s
internal divider. Any remaining
unused input lines should be tied to
ground, as illustrated in Figure 1.
Note that there is a set of configura-
tion pins that’s latched on the *RESET
pin of the S1D13708. These pins are
CNF [7:0] and are hard wired. For
Indirect Mode 68, the CNF [7:0] pins
should be wired to be: 00000111. This
configuration puts the S1D13708 into
Indirect Mode 68: little endian, wait
active low, block divide by one, and
GPIO are outputs. Mode 68 is selected
by tying *BS to ground. Tying *BS to
V
DD
selects Mode 80.
The LCD panel connection truly
depends on the type of panel you’re
Microchip’s P18C452 microcontroller
has 34 I/O lines that can be used as
general I/O lines, 1536 bytes of RAM,
and runs 20 MHz at 3.3 V. Despite
being one of the company’s bigger
chips, you’ll find it easy to use.
The interface between the S1D13708
and P18C452 involves Indirect Mode
68 and requires only four output lines
that act as control signals. Eight bidi-
rectional lines act as the data bus. A
fully functional S1D13708 LCD con-
troller can be attached to the PIC
microcontroller with only 12 I/O
lines. If a 16-bit data bus is desired,
eight more bidirectional lines from the
P18C452 can be connected to DB[15:8]
and one more output line, acting as
EBH, connected to the *WE1 pin of
the S1D13708 (see Figure 1).
As you can see, the hardware con-
nection is simple. The clock and reset
input are the same for the PIC and
Microchip P18C452
CS (RD0)
A0 (RD1)
R/W* (RD2)
EBL (RD3)
D[7:0] (RB[7:0])
CS*
M/R*
RD/WR*
WE0*
DB[7:0]
CLKI
RESET*
DB[15:8]
WE1*
RD*
BS*
AB[16:0]
System CLK
System RESET
Figure 1—The P18C452 interfaces with Epson’s
S1D13708 Indirect Mode 68 interface. Note that when
connecting the S1D13708 *RESET pin, you should be
aware of all conditions that may reset the S1D13708
(e.g., CPU reset can be asserted during Wake-Up
from Power Down modes or during debug states).
Figure 2—Using this schematic, you can interface the Epson S1D13708 to the Microchip PIC17C452. Here is the Epson L2D25001 ND-TFD panel. It’s a pure 3.3-V device.
block of memory. Reading a single
byte of memory requires setting three
address registers and a fourth access to
the Memory Access Start register.
In order to implement the bus
cycles in software you’ll have to refer
again to the Epson web site for the bus
timings. A minimum of three steps
must be implemented in the software
to use the indirect interface. The steps
for an 8-bit data transfer are:
void command_write (char com-
mand_value)
void data_write (char data_value)
char data_read (void)
You can download a C compiler for
the routines from Microchip’s web
site. I found the compiler to be per-
fect for this type of application
because I didn’t require tight opera-
tions and the P18C452 had more pro-
gram space and speed than I needed.
The best thing about the compiler is
that it’s free. Take a look at Figure 3
to see a sequence for reading and writ-
ing the S1D13708. You can also use
the sequence to read memory by
implementing a data_read(). Note that
the memory address is autoincre-
mented after a memory data access
and that the start register REG [C3h]
doesn’t require a data value. You can
also see a C implementation of the
bus cycles in Listing 1.
Photo 1 shows the PIC controller
interfaced to the evaluation board for
the S1D13708. A voltage translator
was used on the PIC because
my team had an EPROM
version of the PIC that
required 5 V for operation.
The OTP PIC17C452 can
operate as a 3.3-V device;
therefore, it will not require
the voltage shifting on the
I/O lines. In addition, all of
the evaluation boards were
designed to be modular. This
gave us a bit of flexibility
when interfacing to various
buses. You can download the
schematic for the evaluation
boards from Epson’s web site.
The Epson L2D25001 ND-
TFD panel was chosen for
the LCD panel. The timing
44
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
going to connect. My office uses
boards that have generic headers that
we can connect to various collections
of panels. But not all panels will use
every LCD pin in the S1D13708 pack-
age. For example, a 4-bit monochrome
panel requires only four of the
S1D13708’s control signals and four of
its data lines. In contrast, an 18-bit
Sharp HR-TFT will use eight control
signals and 18 data lines.
I recommend that you use the
generic connectors to test the differ-
ent panels. After this is done, you can
go ahead and hard wire the final selec-
tion. The panel connector in Figure 2
is for an Epson L2D25001 ND-TFD
panel. I used this panel because it’s a
pure 3.3-V device and it requires no
bias voltage circuitry for panel back-
light. Essentially, this turns the dis-
play circuitry into a simple connector
issue. The schematic for this circuit
was designed to serve as a RS-232 ter-
minal display. The PIC micro listens
to the RS-232 port and passes the data
to the S1D13708’s display memory.
The P18C452 had plenty of horsepow-
er to handle this task, so a smaller
PIC would have been a better choice.
THE INDIRECT INTERFACE
As I mentioned earlier, the
S1D13708 supports various CPU
interfaces. In this project, you are
going to use the indirect interface bus
to connect the PIC and S1D13708. By
using the indirect interface, microcon-
trollers that don’t have a true bus
interface can be connected to
the S1D13708 by implement-
ing software emulation to
toggle the bus cycles.
The indirect interface
comes in two different fla-
vors, the Indirect Mode 68
and Mode 80, both of which
support 8- and 16-bit data
transfers. Additionally, the
two buses are purely asyn-
chronous, which means they
use only chip select as the
control signal to catch the
bus states.
The indirect interface is
based on two existing and
well-known buses. The
Indirect Mode 68 interface
has bus control that’s similar to a
6800, and Mode 80 resembles an 8080.
Furthermore, both modes have been
changed so that they use only a single
address line (A0) to distinguish
between a command access and a data
access. For more information on the
indirect interface mode interface,
please refer to Epson’s web site. The
hardware manual gives clear examples
of the bus cycles and how data is
transferred between a host (i.e., PIC)
and the S1D13708.
BUS SOFTWARE EMULATION
When the S1D13708 is in Indirect
mode it’s not a pure memory-mapped
device. In fact, the protocol of the bus
becomes two addresses (controlled by
an A0 line) that access either the
command register or the data regis-
ter. This makes communication as
simple as issuing a command and
then reading/writing the data register.
To access the S1D13708, this protocol
must be followed.
The S1D13708’s memory is also
accessed through the registers. The
memory address (3 bytes, because
80 KB needs 17 bits to access) has to be
stored in registers 0xC2, 0xC1, and
0xC0. This creates the pointer for
future memory accesses. Then a com-
mand (a write access to the register) is
issued to register 0xC4 to start the
transfer. The address registers are auto-
incremented after each access. The
overhead for reading a large block of
memory is the same as reading a small
Figure 3—For your own applications, you can use this sequence for reading and
writing to the S1D13708’s registers.
Example 1—The sequence for writing the S1D13708 register REG[7Ch] PIP+
Display Start with a value of 28 h is:
command_write(0x7C);
data_write(0x28);
Example 2—The sequence for reading the S1D13708 register REG[26h] and
FPFRAME Pulse Start register 0 is:
command_write(0x26);
value_returned= data_read();
Example 3—The sequence for writing to S1D13708 memory location 200 h with
2 bytes of data is:
command_write(0xC0);
data_write(0x00);
command_write(0xC1);
data_write(0x02);
command_write(0xC2);
data_write(0x00);
command_write(0xC3);
//no data value is needed for the Start register
data_write(0xAA);
//first byte of data written to 0x200
data_write(0x55);
//second byte of data written to 0x201
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
45
requirements of the panel are the
same as a TFT panel, but it has serial
commands that you can send to the
LCD panel itself. These commands
are used to control features such as
partial display. The panel is also a
pure 3.3-V device that doesn’t require
backlight bias voltages. The back-
light is a white LED and the intensity
can be adjusted with the PWM output
of the S1D13708.
SO SIMPLE
This project was simple to execute
because integrating the S1D13708
LCD controller to the PIC didn’t
require the use of too many support-
ing parts. In addition, using a 160 ×
160, 8-bit color TFT panel leaves
about 55 KB of static RAM that the
PIC can access for data storage. There
are speed penalties for using the RAM
because the Indirect Mode interface
bus is emulated with the PIC’s GPIO
lines, but you do get extra storage and
a display controller from a single
S1D13708. Furthermore, the PIC
GPIOs can be regained by multiplex-
ing the signals, and the S1D13708 has
GPIOs and GPOs that the PIC can
use through its registers.
I
Listing 1—Here you can see a C implementation of the bus cycles.
//these are the simplified Indirect Mode 68 interface bus cycles
to mimic on the PIC general I/O pins
#define CommandWriteStep1 0b10010100 //A0 = low, RW = low
#define CommandWriteStep2 0b10011000 //CS = low, EBL = high
#define CommandWriteStep3 0b10010100 //EBL = low,CS = high
#define CommandWriteStep4 0b10110110 //a0 = high, rw = high
#define DataWriteStep1
0b10010110 //rw = low
#define DataWriteStep2
0b10011010 //cs = low,ebl = high
#define DataWriteStep3
0b10010110 //cs = high,ebl = low
#define DataWriteStep4
0b10110110 //rw = high
#define DataReadStep1
0b10111010
//c78NORMAL & ~c78CS | c78EBL; CS = low, EBL = high
//routine to mimic a mode 68 command write cycle
void command_write (char command_value)
{
//command write cycle
PORTB = command_value; //place the register onto the data bus
TRISB = 0;
//make port as output
LATD = CommandWriteStep1;
LATD = CommandWriteStep2;
Nop();
Nop();
Nop();
Nop();
Nop();
LATD = CommandWriteStep3;
LATD = CommandWriteStep4;
LATD = c78NORMAL;
TRISB = 0xff;
//set bus as inputs
}
//routine to mimic an Indirect Mode 68 interface data write cycle
void data_write (char data_value)
{
PORTB = data_value;
//place the register onto the data bus
TRISB = 0;
//make port as output
LATD = DataWriteStep1;
LATD = DataWriteStep2;
Nop();
Nop();
Nop();
Nop();
Nop();
LATD = DataWriteStep3;
LATD = DataWriteStep4;
LATD = c78NORMAL;
//back to original state
TRISB = 0xff;
//set bus as inputs
}
//routine to mimic an Indirect Mode 68 interface data read cycle
char return_data_read;
char data_read (void)
{
TRISB = 0xff;
//make port as output
LATD = DataReadStep1;
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
return_data_read = PORTB;
//place the register onto the data bus
LATD = c78NORMAL; //we can terminate cycle early for speed
return return_data_read;
}
SOURCES
S1D13708 LCD controller,
L2D25001 ND-TFD panel
Epson Corp.
+81 226 52 3131
www.epson.com
P18C452 Microcontroller
Microchip Technology, Inc.
(480) 792-7200
www.microchip.com
HR-JFT Display panel
Sharp Electronics Corp.
(800) 237-4277
sharp-world.com
Peter Chia is an application engineer
with the research and development
group at Epson in the Vancouver
Design Center. He earned a degree in
Electrical Engineering from the
University of Victoria and a technol-
ogist diploma in robotics from
British Columbia Institute of
Technology. You may reach him at
pchia@erd.epson.com.
46
Issue 144 July 2002
CIRCUIT CELLAR
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www.circuitcellar.com
t this moment, I
feel like Mick
Jagger. I can’t get no
satisfaction. I’m looking
forward to using the new PIC18Fxxx
parts because they can run faster and
have quite a bit more RAM and
ROM than the currently available
PIC16Fxxx devices. The problem is
that I can’t get my hands on any of
the new parts. I can’t even get sam-
ples from the Microchip FAE.
However, I’m not going to let the
absence of a part keep me from press-
ing on with this project. Even though
the main piece of programmable
hardware is missing, I still have the
PIC18Fxxx datasheet and program-
ming specifications to work from.
My goal is to produce an inexpen-
sive PIC18Fxxx programmer that
will ultimately allow me to use the
PIC18Fxxx parts in future PIC
Internet/Ethernet projects. And,
because the new PIC18F4xx series is
pin-compatible with the PIC16F87x
devices, I can also expand the
PIC18Fxxx programmer’s capabili-
ties by simply sticking in a
PIC18Fxxx part with more code and
RAM space to replace the PIC16F8xx
part I’ll use to make the original
PIC18Fxxx programmer.
Checking on the Internet for the
availability of PIC18Fxxx parts, I see
that the date has been pushed back
again. So, let’s go ahead with this proj-
ect and be ready to roll when the new
PICs finally hit the street.
A MODULAR APPROACH
My original idea was to construct a
basis, with both firmware and hard-
ware, for a universal programming
platform. After some more thought, I
came to the conclusion that being
global in this project would be a nebu-
lous undertaking. Complex problems
always can be broken down into sim-
pler parts. So, I opted to modularize
the programmer.
Let’s say you’re reading this article
but you never intend to use a
PIC18Fxxx part. What you need right
now is a programmer for a PIC16F628.
The PIC16F628 programming power
requirements are identical to the
PIC18Fxxx devices and the physical
programming pins are also the same.
The differences are with the program-
ming algorithm and the size and
pinout of the programming socket.
The easy thing to do would be to
build up this modular PIC18Fxxx pro-
grammer and throw in some code and
sockets to use a PIC16F628 instead.
For those of you who like to experi-
ment, the modular programmer plat-
form can be broken down into small-
er subassemblies that you can
remove and replace with a better or
experimental circuit by simply pin-
ning out the separate submodules to
larger subassemblies.
I won’t get too modular in this
series, considering that being too
modular adds complexity and cost.
Instead, I’ll stick to a two-module pro-
grammer platform. One module, the
power module, will house all of the
power components. The other mod-
ule, the program module, will contain
the microcontroller, program memory
storage, communications interface,
and any other programming algo-
rithm/target microcontroller-related
hardware. A standard board-to-board
or module-to-module pinout will be
enforced so that power and program
Building a Modular
Programming Platform
Part 1: The Program Module
a
Fred is dreaming of
producing an inexpen-
sive PIC18F
xxx pro-
grammer that will ulti-
mately allow him to
use the new PIC parts
in future PIC Internet/
Ethernet projects.
With the datasheet
and programming
specs in hand, he
takes us through the
first part of his project.
Fred Eady
APPLIED
PCs
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
47
much of the human interface smarts
into the PIC16F877 and use a
HyperTerminal session for uploads,
downloads, and status information.
If the need arises for a more
detailed programming interface, the
standard serial interface leaves the
door open to many possibilities,
including hanging a modem on the
MPP serial port.
The MPP PIC firmware is crafted
using the CCS PIC C compiler. The
CCS C compiler contains a number of
canned routines that handle things
like the PIC16F877 serial port inter-
face and the PIC16F877 pulse width
modulation (PWM) module. It’s possi-
ble that some PIC assembly routines
will have to be mixed with the MPP C
source, but that won’t be a problem
with the CCS C compiler.
There are plenty of good reasons to
use C here instead of a raw PIC
assembler. The key advantage to
using the CCS C compiler is that it is
inexpensive and, thus, allows just
about anyone to modify the MPP
firmware. Also, CCS’s C compiler
supports the PIC18Fxxx family of
devices. That means that all variants
of the MPP firmware can be written
with the same C compiler.
modules can be exchanged with bet-
ter, experimental, or specialized user-
designed modules.
Ultimately, I plan to put the
PIC18Fxxx programmer on profession-
al printed circuit boards. But, I’ll
also produce it in point-to-point for-
mat so you can either build it as you
go or soak up the theory and wait for
the pretty PC boards. Another advan-
tage to modularity is that you can
try various methods and components
and simply plug in that particular
module without having to tear the
whole thing apart each time you
want to make a change or try some-
thing extraordinary. So, I’ll present
all of my hardware gyrations in this
series. That way, you can pick and
choose from any of my ideas or form
your own conclusions and circuits
from my experiences.
Because the PIC18Fxxx program-
mer I will describe and build here
can be adapted, I won’t box it in with
the name of a specific microcon-
troller. So, from now on I will be
designing and building the modular
programming platform (MPP). After
the hardware is in place, I’ll provide
various code sets for differing shades
of PIC microcontrollers.
PROGRAM MODULE—SPIN 1
Spin (iteration) 1 of the program
module will be based on a PIC16F877
microcontroller. I am leaning toward
the PLCC package
because I can reduce the
footprint and cram more
parts onto a smaller
board. As of this writing,
the PIC16F877 is the
most potent flash mem-
ory-based microcon-
troller available from
Microchip. Available in
this case means I can
physically acquire it.
The MPP will be capable
of substituting the
newer pin-compatible
PIC18Fxx2/xx8 micro-
controllers for the
PIC16F877 for possible
future enhancements.
Using the RS-232 serial
port is the easiest and
least expensive method to interface
the MPP to the source of the code that
can be downloaded. The PIC16F877
has an on-chip universal synchronous
asynchronous receiver transmitter
(USART), so all you need to employ
it in this application is the presence
of an RS-232 interface IC. The
MAX232 is a less-expensive RS-232
interface solution, but I’d rather
spend a little more money and install
the Sipex SP233ACP. The stan-
dard MAX232 requires some
additional charge pump capaci-
tors that are already built into
the SP233ACP.
The MPP requires more
than just a simple transmit
and receive line interface.
There are enough RS-232
buffers within the SP233ACP
architecture to provide RS-
232-to-TTL translation for
transmit, receive, and clear-
to-send (CTS) flow control
lines with one buffer in
reserve. Normally, that last
buffer would be put to work
on the request to send (RTS)
line, but in my experience, I
always end up ignoring the
RTS signal and everything
works just fine without it.
The jury is still out on
whether or not I’ll write a
GUI interface for the MPP.
The initial plan is to stuff as
Group
A
control
Group
A
port
A
(8)
Data
bus
buffer
Read/
write
control
logic
Group
B
control
Group
A
port C
upper
(4)
Group
B
port C
lower
(4)
Group
B
port
B
(8)
Power
supplies
5 V
GND
Bidirectional
data bus
D
7
–D
0
*RD
*WR
A
1
A
0
RESET
*CS
I/O
PA
7
–PA
0
I/O
PC
7
–PC
4
I/O
PC
3
–PC
0
I/O
PB
7
–PB
0
8-bit
Internal
data bus
Figure 1—Although slow by today’s standards, the 8255 is easy to use
and widely available for less than $4 in single quantities. That’s probably
why it’s still around.
Figure 2—Running the PIU in mode 0 makes building the control
word second nature. Even though port C is an 8-bit port on its
own in mode 0, it’s still divided between the groups in the control
word definition.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Group B
Port C (lower)
1 = Input
0 = Output
Port B
1 = Input
0 = Output
Mode selection
00 = Mode 0
01 = Mode 1
1x = Mode 2
Group A
Port C (upper)
1 = Input
0 = Output
Port A
1 = Input
0 = Output
Mode selection
00 = Mode 0
01= Mode 1
1x = Mode 2
Mode set flag
1 = Active
Control word
PICING IT APART
The PIC16F877 is equipped with
three 8-bit I/O ports (B, C, and D), a
separate 3-bit E port, and port A—a
6-bit I/O port. Spin 1 of the MPP will
include a 128-KB SRAM that will be
partitioned to house the entire pro-
grammable code content of the device
being targeted. For a PIC18F452, the
required SRAM size comes to 32K of
16-bit wide memory (64 KB of
SRAM) plus additional space for user
ID words and the device configura-
tion word.
At first glance, it would seem that
the PIC16F877 has enough native I/O
to accommodate the 128-KB SRAM’s
17 address lines and eight data I/O
lines considering that I previously
called out 33 I/O lines spread out
over five I/O ports. The problem is
that, in this MPP configuration, at
least two of the port B lines are used
as the programming clock and data
lines. The serial port interface takes
three of port C’s pins. Various other
PIC16F877 I/O lines will be called on
for various control and status duties.
Even more lines will disappear if any
type of external device that
needs to be controlled by the
PIC16F877 is added to the
MPP hardware configuration.
Obviously, there aren’t
enough PIC16F877 I/O lines
to handle the 128-KB SRAM
without the help of an exter-
nal device to add additional
I/O port pins.
There are a couple of
schools of thought when it
comes to expanding the
effective number of PIC I/O
pins. If the application
requires a great deal of output pins
and has plenty of time to service
them, the 74HCT595 serial-in-to-
parallel-out shift register approach
is the best way to go. If you ignore
the master clear pins on each
74HCT595, you can clock out
8 bits of data per 74HCT595 using
only two I/O pins of any PIC I/O
port. But, you have to consider the
negative as well. The downside to
using the 74HCT595 in the MPP
configuration is that, if the
74HCT595 is used to provide the
SRAM address lines, you would have
to either daisy chain three of them or
clock each 74HCT595 individually.
Also, just in case you ever want to
randomly retrieve data from the
SRAM, using the 74HCT595s would
force you to keep up with what’s in
each 74HCT595 so you could clock in
the desired bits. In a daisy chain of
74HCT595s, you would have to clock
in the entire 17 bits of address infor-
mation, and that would occur only
after you made sure you knew where
you were starting and stopping in the
17-bit sequence.
There is no doubt I could make this
happen with the 74HCT595 parts, but
I don’t want to write extra code just to
keep up with where I am in the shift
pattern. I’m not going to totally dis-
count the 74HCT595 as a solution,
but it looks like too much firmware
work coupled with too many parts
shrouded with too much doubt.
Because I’ve temporarily nixed the
74HCT595, that also puts the
74HCT165 parallel-in-to-serial-out
converter on the back burner for a
while. I need a bidirectional data path
48
Issue 144 July 2002
CIRCUIT CELLAR
®
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Photo 1The blank socket at the far right is a placehold-
er. A 40-pin ZIF will eventually take its place. Im consider-
ing putting the nine-pin D shell socket that will become the
serial interface on the power module.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Bit set/reset
1 = Set
0 = Reset
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 B
0
0 0 1 1 0 0 1 1 B
1
0 0 0 0 1 1 1 1 B
2
Bit select
Bit set/reset flag
0 = Active
Don't
care
X X X
Control word
Figure 3This is my favorite 8255 feature. The idea is to offload
some of the control responsibility regarding the I/O from the host
microcontroller.
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CIRCUIT CELLAR
®
Issue 144 July 2002
49
to the SRAM data bus. To accomplish
that with the 74HCT165 as a parallel-
in-to-serial-out input device would
also require another 74HCT595 on the
output side. After doing some
research, I believe I’ll have enough
pins to fully use the PIC16F877 I/O
complement without having to resort
to the 74HCT595 or 74HCT165
devices. So, I won’t bit bang the out-
put of the SRAM or its address pins in
this MPP spin.
Eliminating the serial-to-parallel
and vice versa ideas means I’ll have to
dedicate a full PIC16F877 data port to
the SRAM data bus. It also means I
have to find a part that can supply a
minimum of 17 I/O lines to the
SRAM using a minimum number of
PIC16F877 I/O lines.
One method that came to mind
immediately was to program another
PIC16F877 to be the address line gen-
erator under the control of the master
PIC16F877 via a virtual serial port
that I could establish between the
PIC16F877s. Again, too much work
for little gain. The optimal solution
would be a single off-the-shelf IC that
could share the SRAM data bus and
provide the 17 lines of SRAM address
I/O. All of that in a PLCC package
would be great, too. For the part to be
able to share a bus implies tristate
capability, and hanging lots of compo-
nents off a kindred set of data lines is
what Intel is known for.
LOVE AT FIRST BROWSE
I found the optimal part while
browsing through my old Intel
Microcontroller Peripheral data books.
The 8255 programmable peripheral
interface (PPI) is the answer. I was
able to come up with an 8255 look-
alike in a PLCC package manufac-
tured by NEC. NEC calls it a parallel
interface unit (PIU) (part number
uPD71055L-10). If you believe the
datasheets, the NEC part is slightly
faster (50 ns) than the Intel 82C55A-2
during reads and writes. But, both
parts are functionally identical in
pinout and operation. Because I’ll be
using the NEC part, I’ll refer to the
uPD71055L-10 as the PIU.
The 8-bit bidirectional PIU data
bus resides on the PIC16F877 I/O
port I designated as the SRAM data
bus. Most likely, the PIU and SRAM
data buses will tie up with port D on
the PIC16F877.
Data bus arbitration is controlled by
the PIC16F877 using the active-low
chip select (CS) line on the PIU and
the active-low output enable (OE) line
on the SRAM. The SRAM’s active-low
chip enable (CE) line is tied perma-
nently to ground.
Reads and writes for the PIU are
controlled by its active-low control
signals RD and WR. The PIU RD line
is also connected to the SRAM OE
pin, and the PIU WR line is physically
connected to the SRAM’s write enable
(WE). A high-going RESET signal for
the PIU is assigned to one of the
PIC16F877 I/O pins.
A CLOSER LOOK
Taking a look at Figure 1, you can
see that the internals of the PIU
consist of two groups of registers (A
and B), presenting 12 bits of I/O
50
Issue 144 July 2002
CIRCUIT CELLAR
®
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wide slices. With A16 low, I can store
up to 64 KB of the least significant
bytes of the PIC18Fxxx or PIC16Fxxx
device instructions. Conversely, if I
take A16 high, I have another area of
64 KB that I can put the most signifi-
cant PIC 14- or 16-bit instruction
bytes into. The beauty of this scheme
is that I don’t have to increment the
SRAM address to get 16 bits of PIC
data out of the 8-bit wide SRAM.
For instance, let’s say I need to
store instruction 0x3C83 at SRAM
location 0x00000. First, I store 0x83
at SRAM address 0x00000 with A16
low. Then, I raise A16 and store 0x3C
at SRAM address 0x10000. The PIC
will not use any SRAM area above
0x08000 or 0x18000, because its
ROM area extends to a maximum of
only 32 KB. So, A16 is not in the pic-
ture as far as addressing the PIC
instructions is concerned.
In PIC land, 0x3C83 is the instruc-
tion at ROM location 0x00000. By
simulating 16-bit SRAM using A16, I
can keep the PIC’s logical instruction-
to-address association. That is, the
each. Because I won’t be using the
special function modes of the PIU,
it’s much easier to think of the PIU as
three 8-bit I/O ports (port A, port B,
and port C).
Port C is logically divided into two
groups of four bits. One set of bits
resides in Group A and the other set
of bits belong to Group B. Ports A and
B will be used as SRAM address lines
A0–A15, with A16 being controlled by
a bit from port C. The PIU I/O port
selection is determined by PIU address
lines A0 and A1. An internal PIU
command register is also mapped into
the A0–A1 PIU address space. You can
download a rundown of the PIU pin
assignments and read/write control
logic from the Circuit Cellar web site.
The PIU will operate in mode 0, or
the basic input/output mode. This is
the simplest PIU mode to set up.
Knowing in advance that all of the
PIU’s I/Os will be outputs, the control
word in Figure 2 is easy to fill in. The
sole 1 bit is the mode set flag resulting
in a control word value of 0x80. At
power-up or following a PIU reset, the
PIU defaults to mode 0 with all I/O
pins configured as inputs.
The PIU control word is also used to
access the bit-addressable feature of
port C of the PIU. As you can see in
Figure 3, the least significant bit of the
control word determines if the selected
port C bit is set or cleared. The upper
bits of the lower nibble of the PIU
control word points to the bit to be
toggled. A zero in the most significant
bit of the PIU control word delineates
the bit set command from the mode
set command. I’ll press the bits of port
C into action as power control pins.
IN FULL VIEW
Photo 1 is a preliminary shot of the
MPP. I used the Dallas DS1245 non-
volatile SRAM because I simply didn’t
have any standard 128-KB SRAMs in
the Florida room.
What really matters concerning the
SRAM is how the data will be stored
and retrieved. I need 32K 16-bit words
of storage. Using the SRAM’s A16
address line, I can logically split the
128-KB SRAM into two 64-KB, 8-bit
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
51
Fred Eady has more than 20 years of
experience as a systems engineer. He
has worked with computers and com-
munication systems large and small,
simple and complex. His forte is
embedded-systems design and com-
munications. Fred may be reached at
fred@edtp.com.
SOURCES
PIC C compiler
CCS, Inc.
(262) 797-0455
E-mail: ccs@ccsinfo.com
Microchip Technology Inc.
(480) 786-7200
Fax: (480) 899-9210
www.microchip.com
uPD71055L-10 PIU
NEC Corp.
(800) 338-9549
011-813-3454-1111
www.nec.com
SP233ACP
Sipex Corp.
(978) 677-8700
www.sipex.com
to reduce parts count. I’ll also show
you how to use the PWM module of
the PIC16F877 to generate the high-
voltage programming power supply.
I’m a little nervous about the
PIC18Fxxx datasheet, because I haven’t
had the opportunity to handle the
device and work out the potential
gotchas. So, assuming the PIC18Fxxx
parts will be available before I talk to
you again, I hope to have some real
experience with the PIC18Fxxx parts
to pass on to you. Whether or not the
parts appear, I’ll still perform experi-
ments based on the data in the PIC-
18Fxxx datasheet and knock out some
C code to bring the MPP to life.
I
instruction that will be stored in the
PIC’s ROM at address 0x00000 will
reside in the SRAM at address
0x00000 (low byte) and 0x10000
(high byte), which, when ignoring
A16, logically equates to SRAM
address 0x00000.
Normally, I would store 0x83 at
SRAM location 0x00000 and then
store 0x3C at SRAM location
0x00001. Then, I would have to keep
my mindset focused on converting
the SRAM addressing model to the
PIC addressing model. Partitioning
the SRAM eliminates the brainteaser
and saves cycles as well.
MPP PREVIEW
That pretty much completes the
description of the program module
hardware. I’ve included a schematic
for those of you that want to build
your program module and get ready
for Part 2 of this series (see Figure 4).
Next time, I’ll describe the power
module. The plan is to use switching
power supply technology in an effort
Figure 4Rest assured that there will
be some minor changes made to the cir-
cuit as I begin to write the code.
SOFTWARE
52
Issue 144 July 2002
CIRCUIT CELLAR
®
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his is the final
installment in our
series on the Robot
Conversion Kit (RoCK).
In the past three issues, you’ve learned
how we arrived at the RoCK’s specifi-
cations, how and why we designed the
circuitry, and the scheme we used to
program it. This month, we’ll tie up
the loose ends by describing the
RoCK’s discrete motor driver, explain-
ing the low-level RoCK/host interface,
and walking you through the creation
of a new user-programmed task.
WHAT IS A MOTOR?
Before designing a motor driver,
you have to develop an electrical
model of the motor you wish to con-
trol. So, what’s a motor? A motor is a
device that converts electrical energy
into mechanical energy. There are
dozens of different types of motors,
but the broadest classification divides
them into direct current (DC) and
alternating current (AC). Most robots
are battery-powered and require DC
motors. There are three common types
of DC motors: permanent magnet
(PM), stepper, and brushless. Toy
manufactures tend to use PMDC
motors because they’re cheap and easy
to control.
Figure 1 depicts a simple PMDC
motor. The voltage (E) at the motor’s
terminals can be described by the fol-
lowing differential equation [1]:
where E is the sum of the three volt-
ages across the internal components
of the electrical model. See Table 1
for definitions of the rest of the vari-
ables. As the motor spins, the interac-
tion between the permanent magnet
field and the windings generates a
voltage (V) that opposes the supply
voltage. In this instance, V is known
as the back electromotive force (EMF).
Back EMF voltage is directly propor-
tional to the motor’s speed and is
given by the formula:
As the motor turns faster, V increases.
The motor reaches equilibrium and its
speed becomes constant when the
applied voltage is equal to the back
EMF voltage minus resistive losses.
The motor current (I) is proportion-
al to the total torque produced by
the motor:
When the motor reaches equilibrium
the current is constant, so the follow-
ing term goes to zero:
If you consider only the equilibrium
condition, you can set this term to
zero. Then, by substituting for V and
I
, you arrive at the following equation:
RoCK Specifications
t
In Parts 1, 2, and 3,
Joseph and Ben dis-
cussed the RoCK’s
specifications, circuit-
ry, and programming.
In this final part,
they’ll describe its dis-
crete motor driver,
explain the RoCK/
host interface, and
show you how to cre-
ate a new user-pro-
grammed task.
Joseph Jones & Ben Wirz
FEATURE
ARTICLE
Part 4: Tying Up Loose Ends
Table 1—In our analysis of a PMDC motor we refer to these ten symbols.
E
Terminal voltage
T
L
Shaft torque output
I
Motor current
ω
ω
Motor shaft rotation rate
L
Winding inductance
K
T
Torque constant
R
T
Terminal resistance
K
E
Back EMF constant
V
Back EMF voltage
T
M
Motor torque losses
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CIRCUIT CELLAR
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53
reverse the direction of rotation, we
needed to reverse the polarity of the
terminal voltage. To do this, we imple-
mented an electrical configuration
known as an H-Bridge. An H-Bridge is
constructed from four electrically con-
trolled switches (see Figure 2). With
SW1 and SW4 closed, the motor’s ter-
minal voltage is positive and current
flows from left to right as the motor
turns forward. Conversely, with SW2
and SW3 closed, the terminal voltage is
negative and current flows from right to
left as the motor turns in the opposite
direction. With at least three switches
open, the motor is disconnected from
the battery and doesn’t turn.
We can control motor direction by
using logic components to activate
diagonally opposite pairs of switches.
To control velocity, we then use a
PWM signal to rapidly open and close
the switches.
SWITCHING INDUCTIVE LOADS
Motors aren’t as well behaved as
other components (e.g., resistors and
LEDs). That’s because motors, being
inductors, can store energy and then
inject it back into your circuit in a
destructive fashion.
The voltage induced across an induc-
tor is proportional to the rate of change
of current moving through the induc-
tor. When the current through an ideal
inductor has reached a steady state, the
inductor acts as a short. The equation
for the voltage across an inductor is:
If you want to understand how an
inductor can create a problem, take a
look at Figure 3. When the switch
closes, the current through the induc-
tor increases until it reaches a steady
state. If the switch is then opened, the
And by solving for
ω
you get:
In practice, you might not be able to
compute this equation because you’ll
rarely know the torque and back EMF
constants. You can use a torque gauge,
tachometer, and multimeter to deter-
mine the constants, but it’s usually
unnecessary. The important thing to
remember is that at a given load, a
motor’s speed is proportional to the
terminal voltage and its torque is pro-
portional to the motor current.
MAINTAINING CONTROL
We can control the speed of a
PMDC motor by varying the terminal
voltage (E). For reasons of cost and
efficiency, we don’t usually vary E
using linear circuit techniques.
Instead, designers typically use a pulse
width modulation (PWM) scheme.
With PWM the instantaneous voltage
applied to the motor is either zero or
maximum. The average voltage, how-
ever, is proportional to the PWM duty
cycle. Many microcontrollers, includ-
ing the RoCK’s AVR, have a built-in
facility for generating PWM.
In comparison to controlling the
velocity, selecting the motor’s rotation-
al direction is a bit more involved. In
order to change the sign of
ω
, and thus
M –
+
SW4
SW3
SW1
SW2
V
CC
Figure 2—Here’s an H-Bridge that’s composed of four
electrically controlled switches. It can select the direc-
tion of motor rotation.
Figure 1—A motor can be modeled electrically as an
inductor (L) in series with a resistance (R), and a volt-
age source (V). The voltage (E) at the motor terminals
can be thought of as the sum of the voltages across the
internal components L, R, and V. A voltage (L × dI/dt)
appears across L when you change the current flowing
through the motor. The voltage across R (IR) results
from electrical losses in the motor, and the voltage (V)
appears because the motor also acts as a generator.
V
L
R
E
+
–
Listing 1—This pseudo-code demonstrates how your computer can communicate with the RoCK by
accessing its own serial port and executing a straightforward program.
function Read_RoCK (Addr) //Addr is the address in RAM we wish
to read
Byte_1 = High_Byte(Addr)//the AVR’s RAM requires a 10-bit
address
Byte_2 = Low_Byte(Addr)
Byte_3 = 0 //byte 3 is a dummy byte for the read function
Serial_out(Byte_1)
//send a byte to the RoCK
Serial_in()
//read and ignore the echoed byte to
clear input buffer
Serial_out(Byte_2)
Serial_in()
Serial_out(Byte_3)
Serial_in()
Return Serial_in()
//the RoCK reports the value stored
at Addr
end
function Write_RoCK (Addr, Data)
//store data at Addr in RAM
Byte_1 = 0x80 bitwise_OR High_byte(Addr)
//High bit set indicates write operation
Byte_2 = Low_Byte(Addr)
Byte_3 = Data //third byte is data in write operation
Serial_out(Byte_1)
Serial_in()
Serial_out(Byte_2)
Serial_in()
Serial_out(Byte_3)
Serial_in()
Return Serial_in() //The RoCK reports the value now stored
at Addr
end
collapsing magnetic field around the
inductor induces a large voltage spike.
The result is a large current change
(dI) over the short time (dt), and a
large potential at V
SW
. This voltage
spike, known as inductive kickback,
can easily exceed the manufacturer’s
ratings of the power-switching device.
However, we can clamp this kickback
voltage to a safe level by connecting a
reverse-biased diode across any switch
that controls an inductor. Because
motors have large inductance, clamp-
ing diodes play an important role in
the design of any motor driver.
A PRACTICAL DESIGN
Now that you understand the basic
concepts, we’ll move ahead and
describe the RoCK’s motor driver (see
Figure 4). We began the design of an
H-Bridge driver by selecting the physi-
cal components needed to create the
abstract switches shown in Figure 2.
Generally, PMDC motor drivers are
Table 2—The RoCK
behaviors use these
parameters to compute
outputs. Parameter values
are copied from flash
memory or EEPROM and
held in RAM during pro-
gram execution. The RAM
address of a particular
parameter is computed by
adding the appropriate off-
set to the base address
given by a constant called
parameter.
used for power switching applications.
However, the impressive V
CE(SAT)
of the
Zetex parts made these bipolar tran-
sistors suitable for our application.
By choosing PNP transistors Q10
and Q14 for the driver’s high side, we
simplified our design. If we had used
NPN transistors, we would’ve had to
drive their bases at a voltage higher
than the power rail. Although PNP
transistors are less efficient then their
NPN counterparts, the Zetex units
met our requirements.
Q6 and Q7 form a logical AND gate
requiring both the PWM and direction
signal to be high for the motor to
receive a positive voltage at its termi-
nals. Q22 performs a logical inversion
of the DIR signal. With PWM high
and DIR low, the motor receives a
negative voltage at its terminals. With
Q6 and Q7 turned on, current flows
out of the base of Q10, through Q6
and Q7, and into the base of Q15. The
base drive current is limited by R32,
and given by the following formula:
The selection of the base resistor
value was a compromise between
providing adequate base drive for the
power transistors and maximizing
efficiency at higher battery voltages.
In the previous formula, you see that
the minimum base current occurs at
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CIRCUIT CELLAR
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implemented by using either bipolar
transistors or MOSFETs in the power
stage driver. Compared to transistors,
MOSFETs offer better performance
and lower resistive losses. However,
they’re more expensive and have more
complex control requirements.
The bipolar design described here
delivers a continuous current of
300 mA per motor, and accepts a bat-
tery motor supply voltage range of 4 to
15 VDC. (Note that the motor current
supplied by the H-Bridge driver is lim-
ited by the specifications of the driver
transistors. The production version of
the RoCK may use higher current
transistors.) By avoiding MOSFETs we
reduced both cost and board space.
The 300-mA continuous current rating
is adequate for the many RC cars
using alkaline AA or 9-V batteries.
Zetex produces a series of capable
SOT-23 bipolar transistors. We used
the Zetex FMMT489TA for the low
side NPN transistor (Q11 and Q15),
and the Zetex FMMT589TA for the
high side PNP transistors (Q10 and
Q14). Both transistors offer a V
CE(SAT)
of
less than 200 mV at:
I
C
= 300 mA
The low V
CE(Sat)
rating reduces the max-
imum power dissipation to 60 mW for
each of the transistors. Because of their
high thermal resistance, SOT-23 pack-
age bipolar transistors aren’t generally
V
CC
I
ON
V
SW
Figure 3—The action of an inductor is to oppose
changes in the current flowing through the inductor.
When we attempt to stop the current, I
ON
, flowing
through the inductor by opening the switch, the induc-
tor reacts by rapidly increasing the voltage V
SW
.
Offset
Name
Description
Offset
Name
Description
0
pg_speed
Global max robot speed
20
pv_i
1
pd_dance_index
Dance selector
21
pr_time
Time between random events
2
pd_dist_fact
Time/distance ratio
22
pr_dur
Duration of random event
3
pi_a
The parameters pi_a
23
pc_dir
Robot turn angle
4
pi_b
through pi_i are the
24
pe_backup
Escape backup time
5
pi_c
coefficients of a matrix
25
pe_spin
Escape spin time
6
pi_d
that transforms left and
26
pe_fwd
Escape forward time
7
pi_e
right IR detector inputs
27
reserved
Reserved for future expansion
8
pi_f
into left and right velocity
28
reserved
9
pi_g
and action
29
reserved
10
pi_h
30
pj_angle
Joystick drive angle
11
pi_i
31
pj_speed
Joystick speed
12
pv_a
The parameters pv_a
32
pj_active
Joystick active
13
pv_b
through pv_i are the
33
pb_tempo
Tempo of buzzer tune
14
pv_c
coefficients of a matrix
34
pb_select
Buzzer input source
15
pv_d
that transforms left and
35
pee_high_addr
High byte of EEPROM Addr
16
pv_e
right photocell values
36
pee_low_addr
Low byte of EEPROM Addr
17
pv_f
inputs into left and right
37
pee_data
Data for EEPROM
18
pv_g
velocity and action
38
pee_flag
Write EEPROM data flag
19
pv_h
39
px_frob
Map user potentiometer value to parame-
the minimum battery voltage. Both
the PNP and NPN transistors have a
beta (gain) of at least 50 throughout
their operational range. A 330-
Ω
resistor maintains the required base
drive current of at least 6 mA across
the voltage range.
With a 4-V battery, the base current
would be 7 mA; with a 15-V battery,
the current would be 40 mA. A higher
battery voltage reduces the motor dri-
ver’s efficiency by pushing more cur-
rent into the base than is necessary.
We expected that most users would
employ low-voltage batteries, so we
optimized the driver for the lower
range. The quiescent current is unaf-
fected by the base resistor choice.
Shoot through often creates perplex-
ing problems for discrete H-Bridges.
Shoot through is a transient condition
that occurs when the high and low
sides of the H-Bridge are unintention-
ally turned on simultaneously. For
example, suppose the motor in
Figure 2 is going forward (SW1 and
SW4 are on) and the direction is sud-
denly reversed (SW1 and SW4 turn off
while SW2 and SW3 switch on). If, at
the time of reversal, SW3 turns on
faster than SW4 turns off, then there
is a momentary short from the power
rail to ground. In the best-case sce-
nario, this situation results in wasted
power. In the worst case, transistors
are destroyed.
Supplementary components can be
added to the circuit to protect against
shoot through. These components
would provide hard-wired time delays
that turn the drive transistors on and
off in a definite order. Integrated motor
driver ICs use this method. But, we
chose the lower-cost approach by
adding complexity to the software
rather than the hardware. Whenever
the motor direction is reversed, the
RoCK’s software outputs a zero on the
PWM line for 1 to 2 ms and then
restores the commanded PWM value.
Thus, motor direction changes only
when the power is off.
HOST INTERFACE
We turn now to the RoCK/host
computer interface. Ultimately, you’ll
benefit from a host computer-based
software module that will monitor the
RoCK’s internal variables and simplify
programming. That software hasn’t
been written yet, however, we’ll
describe the low-level interface that it
will be based on.
The AVR uses a Harvard architec-
ture that establishes separate memo-
ry spaces for program and data.
Program memory consists of the
RoCK’s software instructions and
certain constant values. The AVR’s
flash memory provides program stor-
age, and it can’t be changed during
program execution. The data address
space is located in the AVR’s 512 bytes
of RAM, which contains the AVR’s
control registers, stack, and all of the
RoCK’s variables. There’s also a third
memory space, 512 bytes of EEP-
ROM. Special instructions provide
access to this memory.
To compute their outputs, the RoCK’s
behaviors incorporate one or more
adjustable parameters. The RoCK’s
tasks specify values for these behavior-
effecting parameters (see Table 2). Built-
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CadSoft Computer, Inc., 801 S. Federal Highway, Delray Beach, FL 33483
Hotline (561) 274-8355, Fax (561) 274-8218, E-Mail : info@cadsoftusa.com
Schematic Capture • Board Layout
Pay the difference for Upgrades
You can use EAGLE Light for testing and
SMD pads can be rounded or round
Different pad shapes for Top, Bottom,
or Inner layers
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Issue 144 July 2002
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in tasks store default parameter
values in flash memory, and
user-programmed tasks keep
initial values in EEPROM. In
either case, parameter values
are copied to RAM at startup.
To program a user task you
must store parameter values in
EEPROM. To change robot
behavior on the fly, the host
computer writes parameter val-
ues to RAM.
All interactions between the
RoCK and host computer are
conducted using the 3-byte
serial protocol (3BP) described in
Part 2 (Circuit Cellar 142). The 3BP
reads and writes locations in RAM.
To communicate with the RoCK,
your computer must access its own
serial port and execute a simple pro-
gram. You can write the program in
Visual Basic, C, Lisp, or another
familiar language. Listing 1 shows
the pseudo-code we wrote.
The simulated code in Listing 1
assumes the availability of functions
called
Serial_out and Serial_in.
These functions send and receive
1 byte of data to the serial line. The
code also relies on a function to select
the highest two bits of a 10-bit
address,
High_Byte, and the lowest
eight bits,
Low_byte, as well as a func-
tion to OR together two bytes, called
bitwise_OR.
MONITOR AND CONTROL
Monitoring key locations is simple
when you use the functions described
previously. Suppose you want the cur-
rent value of the right photocell.
From Table 3 you can see that
photo_right has an offset of one. This
means that the value is located in
RAM at the location sensor plus one.
In the current compilation, sensor has
the value 0x0BC. Therefore, you call
Read_RoCK (0x0BD) to get the value
of the right photocell. Communicat-
ing with the RoCK at 9600 bps and
allowing four byte transfer times to
send three and receive one byte
means that the host can get an updat-
ed value for any sensor reading in a
minimum of about 4 ms.
We can also use the host computer to
directly control our robot. To do this,
we used the Select button and user
potentiometer to select the Remote
task. The remote task calls the
Joystick behavior, and Joystick
decides the robot’s speed and direction
by watching the parameters pj_angle,
pj_speed, and pj_active (see Table 2).
The host computer can directly con-
trol the motion of the robot by writ-
ing values to these variables via the
Write_RoCK function. To obtain the
address in RAM of a parameter, we
added the base address parameter to
the offset given in Table 2.
PROGRAM A TASK
Monitoring and controlling the
robot directly from your host comput-
er is a matter of reading or writing
addresses in RAM. Programming a
user task means storing certain values
in nonvolatile EEPROM. To demon-
strate the latter, we will create a
new user task called BumpEm.
BumpEm is a simple task that
makes the RoCK move in a large
circle. If the robot bumps into
something, the beeper sounds,
and the RoCK backs up and
chooses another direction. We
need only two primitive behav-
iors, Cruise and Escape, to com-
pose this task.
The Cruise behavior makes
the robot move, ignoring all sen-
sors. Cruise uses a parameter,
called pc_dir, that tells it which
way to move. When the value of
pc_dir is 128, the Cruise behavior
sends commands to the robot’s
motors that produce a forward
motion. If the value is 64, Cruise
makes the robot spin in place to the
left; a value of 148 will make the
robot spin to the right; and a value of
zero or 255 will make the robot back-
up. Thus, pc_dir indicates the turn
angles for the robot. And we’ll choose
a value of, say, 130 to make the
RoCK arc a little to the right.
The Escape behavior decides when
the robot should try to escape from a
collision with another object. The
actions of the Escape behavior are
specified by three parameters:
pe_backup, pe_spin, and pe_fwd.
These three parameters determine
how long the robot should backup,
spin in place, and move forward after
Table 3—Functions of the RoCK constantly update the value of these
real and virtual sensors. Values are stored at consecutive fixed locations
in RAM and are accessible to the host computer. Values are offset from
the base address constant called sensor.
Offset
Name
Description
0
Photo_left
Left photocell
1
Photo_right
Right photocell
2
Motor_bat
Voltage of motor battery
3
Logic_bat
Voltage of logic battery
4
User_pot
Setting of user potentiometer
5
IR_detect
Left and right IR detection bits
6
Bump
1-bit collision detection
7
User_button
State of user button
Figure 4—The RoCK’s discrete motor driver is implemented using small SOT-23 bipolar transistors. Reverse-
biased diodes between the emitter and collector of each driver transistor (Q10, Q11, Q14, and Q15) protect the
transistor from destructive motor-induced voltage spikes. Transistor pair Q6 and Q7 and also Q18 and Q19 form
AND gates. These gates select diagonally opposite pairs of driver transistors and thus motor direction. The selec-
tion is made by the DIR-A signal along with the inverse of DIR-A created by Q22. The PWM-A signal then rapidly
switches the selected pair to control motor speed.
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CIRCUIT CELLAR
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Issue 144 July 2002
57
a collision. The definitions
for these values are such
that we can make the
robot backup for 250 ms by
setting pe_backup to 16,
spin for 500 ms by setting
pe_spin to 31, and then
give up control immediate-
ly by setting pe_fwd to
zero.
There are two more
important parameters:
pb_select, which is the
beeper control parameter,
and px_frob, which is the
index of the parameter
that receives input from the user
potentiometer. The beeper behavior
is written so that we can make the
beeper sound whenever a collision
occurs if we write a three to
pb_select. We will set px_frob to the
index of pg_speed (zero) to make the
user potentiometer control robot
speed. If we instead set px_frob to
the index of pc_dir (23), then the
user potentiometer would control
the drive angle used by the Cruise
behavior. Rather than controlling
speed, the user potentiometer could
be used to make the robot drive in
various directions.
We now know the parameter val-
ues needed for the BumpEm task.
But we also need to specify the
behavior priority list. The highest
priority behavior must be Escape,
which will control the robot during a
collision. Cruise gets the second high-
est priority slot. To instantiate this,
we must write the indices
of Escape and Cruise, six
and five respectively, to
the user priority list of
user task one (see Table 4).
To store our choices in
EEPROM, we access the
RoCK’s EEPROM writer
function by writing special
registers that were created
in RAM. For example, the
first value we want to set is
the highest priority behav-
ior in user task one.
Referring to Table 4, you
see that user task one is
at location 0 in EEPROM. The value
we want to store here is six, the
index of the Escape behavior. To do
this, we use Write_RoCK to write
the high part of the EEPROM address
(zero) to parameter pee_high_addr.
We write the low part of the address
(also zero) to pee_low_addr, the data
(six) to pee_data. Finally, we write a
one to pee_flag. As soon as this final
step is taken, the data is actually
stored in EEPROM.
Table 4—The AVR’s 512 bytes of EEPROM memory are mapped as shown.
Address range
Description
0–9
Priority list for user program 1
10–49
Parameter list for user program 1
50–59
Priority list for user program 2
60–99
Parameter list for user program 2
100–109
Priority list for user program 3
110–149
Parameter list for user program 3
150–159
Priority list for user program 4
160–199
Parameter list for user program 4
200–349
User-programmed song (150 notes maximum)
350–500
User-programmed dance (150 steps maximum)
500–509
Reserved
510
Steering configuration flag, differential drive versus drive/steer
511
Index of the most recent user-selected task
SOLUTIONS CUBED (530) 891-8045 PHONE WWW.SOLUTIONS-CUBED.COM
58
Issue 144 July 2002
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®
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Ben Wirz also grew up in a small
town in the Missouri Ozarks. He
studied physics and electrical engi-
neering at Washington University in
St. Louis, and graduated in 1997. He
is currently employed as a senior
electrical engineer by iRobot in addi-
tion to running his company, Wirz
Electronics. You may reach him at
ben@wirz.com.
REFERENCE
[1] J. Jones, A. Flynn, and B. Seiger,
Mobile Robots: Inspiration to
Implementation, 2nd ed.
, A.K.
Peters, Ltd., Natick, MA, 1999.
Joseph L. Jones grew up in a small
town in the Missouri Ozarks. He stud-
ied physics at MIT and received a BS
in 1975 and an MS in 1978. He took a
trip around the world, worked at the
MIT Artificial Intelligence Lab, and is
now senior roboticist at iRobot Corp.
You may reach him at jlj@irobot.com.
RESOURCE
Application Notes,”
www.pittmannet.com.
SOURCE
FMMT489TA, FMMT589TA
Zetex Semiconductors
44 161 622 4444
www.zetex.com
All of the other values we want to
store can be saved in the same fash-
ion. And when they’re finally writ-
ten, we’ll have created the new
BumpEm task. We can have the
RoCK run this task by pressing the
user button and twisting the user
potentiometer just as we would do for
any of the built-in tasks.
SERIES SUMMARY
We hope you’ve found our series to
be instructive and that you’re now
eager to build a robot. There are many
resources for learning more about
robots. Searching the ’Net will return
hundreds or even thousands of hits.
You may find a robot users group or a
robot club in your area. Joseph’s book,
Mobile Robots: Inspiration to
Implementation
, is designed to help
you get started in robotics. And final-
ly, please check for new develop-
ments and more information about
the RoCK on our web site.
I
Authors’ Note: We plan to offer the
RoCK for sale. Please check our web
site, www.wirz.com/rock/, for avail-
ability and additional information.
to be used as a smart SPI peripheral to
provide seamless communication over
Bluetooth
Versatile Communications Card for
Linux
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®
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he precise con-
trol of electric
motors is becoming
more popular and afford-
able because of specific enhance-
ments in general-purpose 8-bit
microcontrollers. In this article,
we’ll discuss the type of hardware
feature that has been added to a low-
cost microcontroller to improve its
motor control capability.
A major problem facing designers
of motor controllers is the source of
distortion that’s common to power
stages using totem-pole transistor
configurations driving inductive
loads. On AC induction motors run-
ning open loop, the problem typical-
ly manifests itself as poor low-speed
performance (e.g., torque ripple and
rough operation).
The MC68HC908MR32 microcon-
troller solves the problem by sensing
the motor phase voltages during the
dead-time intervals and modifying
the modulation waveform to cancel
the effects of the distortion. This
results in quieter and smoother run-
ning motors.
The main features of the microcon-
troller are the 32 KB of flash EEPROM
program memory and 768 bytes of
RAM (see Figure 1). There is also an
analog-to-digital converter used to
interface to signals such as sensor
inputs and other analog waveforms.
There are two serial communications
systems: the Serial Peripheral
Interface (SPI), which is synchronous,
and the Serial Communications
Interface (SCI), which is asynchro-
nous. The LVI is a low-voltage inhibit
module with software-selectable trip
points, and there are two timer mod-
ules that each offer a variety of hard-
ware timer functions. The specific
functions that have been implemented
to facilitate the low-distortion motor
control are included in the pulse
width modulator module.
DEAD-TIME DISTORTION
To drive a three-phase electric
motor, a six-transistor inverter circuit
is commonly used. Most voltage-
sourced inverters require a dead time
to be inserted between the turning off
of one transistor in a half-bridge, and
the turning on of its complementary
device. Otherwise, both transistors in
a half-bridge may be on at the same
time, which would destroy the circuit
by shorting together V
DD
and ground.
By inserting this dead time, a dis-
tortion is introduced in the output
voltage and current waveforms when
the inverter is driving an inductive
load (such as a motor). This distor-
tion, however, can be satisfactorily
corrected in most situations. By
using a Hall Effect current sensor or
other current sensing device, correc-
tion waveforms can be generated that
are synchronous to the motor phase
currents and applied to the PWM sig-
nals. There is also a sensorless tech-
nique that accomplishes this with-
Dealing With Motor
Control Dead-Time
Distortion
t
Dead-time distortion
can be problematic
when you’re trying to
design a motor con-
troller. But that does-
n’t mean you have to
settle for noisy, rough-
running motors. Ross
and David explain
there are inexpensive
enhanced microcon-
trollers that can cor-
rect distortion.
Ross Bannatyne &
Dave Wilson
FEATURE
ARTICLE
CPU
32-KB
Flash memory
EEPROM
768-byte
RAM
LVI
Timer
A
Timer
B
SCI
ADC
PWM
(Low distortion)
SPI
Figure 1—A diagram of the MC68HC908MR32 shows
its 32 KB of flash memory and 768 bytes of RAM.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
61
subtracting n from d1, we
obtain the distortion voltage
that’s actually impressed
across the phase 1 leg of the
load, which is shown as the
bottom waveform of Figure 4.
This voltage sets up a current
in that phase that is a func-
tion of the load impedance.
When the original sine wave
current is added back in by
superposition, the result is a
current waveform with
clipped peaks (see Figure 3).
In fact, under certain condi-
tions when the distortion
waveform is large with
respect to the modulation
waveform, the distortion can
actually cause the current to
dip at its peaks.
PROBLEMS WITH DISTORTION
Several serious problems can arise
because of dead-time distortion. The
amplitude of the distortion per unit of
bus voltage is equal to the ratio of the
dead time to the PWM period. Because
dead time is a system parameter that
is usually fixed in accordance with the
switching characteristics of the power
devices, the problem is usually asso-
ciated with higher PWM frequencies.
In some cases, you will specify a
out the need for current sen-
sors. This feature has been
integrated into the
MC68HC908MR32 micro-
controller. Thus, the benefits
of distortion correction can
be brought to the arena of
low-cost motor control appli-
cations that cannot afford the
more expensive current sens-
ing techniques.
Figure 2 illustrates a half-
bridge circuit composed of
IGBTs that generate a
desired PWM output wave-
form with a 50% duty cycle.
Note that with no dead
time, this could easily be
achieved by turning on the
top transistor for half of the
cycle, and turning the bot-
tom transistor on for the
remainder of the cycle. However,
with dead time inserted, the on
times of both the top and bottom
transistors are shortened evenly, so
neither the top nor bottom PWM sig-
nal corresponds to a 50% duty cycle.
Because of the inductive effects of
the load during the dead-time inter-
val, the pulse width of the output
voltage will be effected. It will be
either larger or smaller than desired
(depending on current polarity) by an
amount equal to one dead-time inter-
val. This in turn causes an offset in
the average output voltage. After the
voltage waveform has been effected,
the current waveform will be distort-
ed as well. You can see a depiction of
this in Figure 3.
To understand the shape of the
current waveform, it’s necessary to
consider the distortions and interac-
tions of all three phases. If we
assume a steady state load, it’s safe to
also assume that the angular separa-
tion of each line current is 120°. The
distortion voltage is 180° out of phase
with the current for each phase, so
each of the distortion waveforms are
also separated by 120°, as is illustrat-
ed in Figure 4.
Assuming the motor load is linear,
superposition can be used to analyze
the system response to the distortion
alone (i.e., the modulation signal
equals zero). Under this condition, if
we assume that the motor load is bal-
anced, we can average the three dis-
tortion voltages to obtain the motor
neutral voltage n. Unlike three-phase
sine waves, the distortion waveforms
don’t result in a neutral voltage of
zero over time. Instead, it’s a square
wave with transitions every 60°.
For the sake of this analysis, assume
that the motor is a three-phase y con-
nected load (although the results apply
equally to delta connected loads). By
V+
V–
Desired load
voltage
PWM to top
transistor
PWM to bottom
transistor
Actual load
voltage (for i+)
Actual load
voltage (for i–)
V+
i+
i–
V–
Dead time
Figure 2—During dead time, load inductance defines voltage to keep inductive
current flowing through the diodes. Note how dead time affects the pulse width
of the inductive load voltage.
Voltage with correction disabled
Current is
positive
Current is
negative
Current with correction disabled
2 V Peak-to-peak
12 V Peak-to-peak
Figure 3—As you can see, voltage and current distortion result from dead time.
these signals. With no distortion
correction applied, the register
chosen for each half-bridge driv-
ing a motor phase does not
change during the course of opera-
tion, and defaults to an odd num-
bered PWM value register. When
correction is enabled, the PWM
module toggles between two
PWM registers for each motor
phase. One when the current
polarity for that phase is positive,
and the other when it’s negative.
The waveforms of Figure 5 are
obtained by programming one reg-
ister with the desired pulse width
plus the dead time, and the other reg-
ister with the desired pulse width
minus the dead time.
In actuality, to obtain an output
pulse width delta of plus or minus one
dead time on the MC68HC908MR32
when using Center Aligned mode,
the correction value should be plus
or minus one-half of the value in the
dead time register. This is because
the PWM resolution in Center
Aligned mode is one-half that of
Edge Aligned mode.
An economical way to measure the
current polarity for each phase is to
use the current polarity sense inputs
on the ’MR32. These three pins are
used to monitor the PWM voltage
waveforms supplied to each terminal
of a three-phase motor. Each input is
sampled during the dead time of the
PWM signals associated with that
motor phase. If the input is high dur-
ing the dead time, the current polarity
62
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
higher PWM frequency to mini-
mize the total harmonic distor-
tion (THD) without realizing that
the distortion from dead time
actually gets worse.
Another problem is that voltage
distortion causes current distor-
tion, the result of which is torque
pulsations felt on the motor shaft.
Under certain conditions, this can
translate into stability problems
between the motor and drive.
Unlike the modulation signal
that is purposely impressed upon
the motor windings, the ampli-
tude of the distortion is not affected
by the modulation index. This means
that the problem, when viewed from a
signal-to-noise perspective, is most
severe when the voltage is small. On
an AC induction motor, this occurs
when the motor revolutions per
minute are also small, and the
momentum of the rotor cannot
smooth out the torque pulsations,
making them even more apparent.
Another common problem is that
the distortion is synchronous with the
motor current and 180° out of phase
with it. At low frequencies, this
effect combines with the stator resis-
tor losses to further reduce the
motor torque. Over-modulation in
the form of a voltage boost can be
used to mitigate this problem.
However, the torque pulsations from
the distortion are still present.
The previous analysis is based on
the supposition that the distortion
waveform is perfectly rectangular.
There can be variances from this
premise that have an effect on the cor-
rection technique and make it even
more complex to correct for.
CORRECTING WITH PWM
Because the distortion effect from
dead time can be fairly well character-
ized, it stands to reason that the cure
should be equally straightforward.
This is true, with the exception of a
few second-order effects. The output
waveform has a distortion with char-
acteristics that can be closely approxi-
mated, so the answer is to counter-
modulate the original PWM signal to
provide noise cancellation. In other
words, a correction signal is superim-
posed on top of the sine wave signal in
the processor to cancel the output dis-
tortion. The distortion signal resem-
bles a square wave; therefore, the cor-
rection term is also a square wave.
And because the distortion signal is
synchronized to the current waveform
for that phase, the correction term
also must be synchronized to the
same current waveform.
Another way to view the correction
process is illustrated in Figure 5.
Recall from Figure 2 that the
dead time was balanced
between the top and bottom
PWM signals. For that par-
ticular example, a 50% duty
cycle was desired. With the
insertion of dead time, the
top and bottom PWM sig-
nals had their on times
reduced by an equal amount
to something less than 50%.
The MC68HC908MR32
always uses a single PWM
register to derive the top and
bottom signals for each tran-
sistor in a half-bridge, and it
automatically inserts a pro-
grammable dead time into
i
2
i
3
d
1
d
2
d
3
n
d
1
- n
i
1
Figure 4—These are calculated distortion waveforms.
Desired
load voltage
Top
PWM
Bottom
PWM
Actual
load voltage
V+
Gnd
i+ condition
i– condition
Figure 5—This example of distortion correction is
accomplished by the redistribution of dead time.
0.5-hp 3-phase motor
PWM Frequency = 7.3 KHz
Output :
w = 1.7 Hz
Figure 6—Here’s a partially corrected current waveform.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
63
is determined to be neg-
ative, and vice versa.
This information can
then be used by hard-
ware in the PWM mod-
ule to automatically tog-
gle between one of two
PWM registers, as dis-
cussed earlier.
ZERO-CROSSING
DISTORTION
When the distortion is
corrected in this man-
ner, the current wave-
form in Figure 6 is
obtained. The modula-
tion index is scaled, so
the current peak ampli-
tude matches that of
Figure 3. Otherwise, the
same modulation index
results in a 50% increase
in the peak amplitude,
which demonstrates the
severity of the distor-
tion. Although most of the distortion
is gone, some still exists at the zero
crossings. This causes torque pulsa-
tions that can be detected on the
motor shaft. To eliminate this distor-
tion, you need to go beyond our first-
order explanation of the distortion
source in order to understand what’s
happening to the system during the
current zero crossings.
Up to now, we’ve assumed that the
distortion waveform is a perfect rec-
tangular wave shape, and therefore has
“snappy” rising and falling edges.
Related to this premise, we have also
implied that the inverter output volt-
ages are either high or low at any
given time, including the dead-time
intervals. These assumptions are true
when the current amplitude is high.
However, under low-current condi-
tions, which occur near the zero cross-
ings, the inductor is less aggressive in
snapping the voltage high or low.
Presumably, this is because of para-
sitic capacitance in the motor and
drive, which can support the induc-
tor’s low current flow. Prior to the
dead-time interval, if the output volt-
age was already driven in the direc-
tion that the inductor would drive it
based on the current polarity, this
phenomenon is not observable. The
problem occurs when the other tran-
sistor is on and the inductor must
drive the output voltage through the
full power supply range during the
dead-time interval.
The net effect is that the voltage
waveform does not transition instanta-
neously when the current polarity
changes. Instead, a softer transition
occurs that takes the edge off of the dis-
tortion waveform. Figure 7 illustrates
the voltage waveforms out of one half-
bridge of the inverter under
various current conditions.
We now draw a distinction
between the dead-time inter-
val before the assertion of the
top PWM and the dead-time
interval before the assertion of
the bottom PWM. If you com-
pare the two dead time regions
in a given PWM period, you’ll
notice that when the current
magnitude is large, the volt-
ages during the dead times are
the same regardless of polarity.
However, when the current
magnitude is small, the volt-
age waveforms are different
in the dead-time intervals.
This suggests a strategy for
detecting when the cur-
rent waveform is
approaching a zero
crossing, and acting
before it actually occurs.
What you need is a
waveform discriminator
that can tell the differ-
ence between these
voltage waveforms.
Figure 8 illustrates a
distortion correction
system acting on a sin-
gle phase that incorpo-
rates this sort of voltage
sensing technique. By
using either hysteresis
or a simple low-pass fil-
ter, the sensor detects
whether or not the load
inductor aggressively
snaps the voltage wave-
form during the dead-
time intervals. At the
end of each dead time
region, the comparator
output is sampled by the D-type flip-
flops, and the results are stored for
both dead-time intervals. If the induc-
tor cleanly snaps the voltage wave-
form, then both results will agree
with each other.
For example, if both sampled out-
puts are low, the current is large and
flowing out of the inverter.
Conversely, when both sampled out-
puts are high, the current is large and
flowing into the inverter. However,
under low-current conditions (regard-
PWM to
top transistor
PWM to
bottom transistor
Load voltage
(for high i+)
Load voltage
(for low i+)
Load voltage
(for high i–)
V+
i+
i–
Dead-time interval before
the assertion of the top PWM
V–
Dead- time interval before
the assertion of the bottom PWM
Load voltage
(for low i–)
On
Off
On
Off
On
Off
On
Off
On
Figure 7—The load voltage waveforms look as shown under various current conditions.
V+
i+
i–
D
Q
Processor
DT1
DT2
D
Q
Memor
y location $0024
PWM1
PWM2
PWM1
PWM2
Voltage
sensor
τ
DT1
DT2
Load current condition
0
0
High amplitude i+
High amplitude i–
Low amplitude, either polarity
1
1
0
1
or
Figure 8—Take a look at this sense scheme for optimized dead-
time distortion correction.
value can be toggled
before the current
begins to flatten out.
RESULTS OF COR-
RECTION
Figure 9 illustrates
the results of dead-time
distortion correction
using this technique
and the hardware on
the MC68HC908MR32.
By using the voltage
information obtained
during the dead time,
the software can count-
er-modulate the PWM
waveforms to cancel
the distortion. We
measured these results
from a 0.5-hp three-
phase motor with a
PWM frequency of
7.3 kHz with 3-µs dead time.
I
64
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
SOURCE
MC68HC908MR32 Microcontroller
Motorola, Inc.
(847) 576-5000
www.motorola.com
Ross Bannatyne graduated from the
Electrical and Electronic Engineering
honors program at the University of
less of polarity), the sampled results
will be different, indicating to the
control algorithm that a current zero
crossing is looming in the near future.
Therefore, the distortion correction
Figure 9—By using the voltage information obtained during the dead
time, the software can counter-modulate the PWM waveforms to cancel
the distortion. The output waveforms were obtained with the voltage sen-
sor using hysteresis.
Current with correction enabled
0.5-hp 3-phase motor
PWM Frequency = 7.3 KHz
Output: w = 1.7 Hz
2 A Peak-to-peak
12 V Peak-to-peak
Voltage with correction enabled
David Wilson earned a B.S.E.E. from
John Brown University in 1979 and
an M.S.E.E. from the University of
Wisconsin in 1986. From 1979 to
1990, David held design engineering
positions with several companies and
worked in fields ranging from motor
control to nuclear pulse measure-
ment. David currently performs vari-
ous field applications assignments for
Motorola. You may reach him at
david.l.wilson@Motorola.com.
Edinburgh, Scotland in 1991, and has
attended the University of Texas at
Austin for an executive MBA pro-
gram. He is currently the Americas
distribution manager for the 8/16-bit
Division of Motorola SPS. You may
write to him at r11607@email.
sps.mot.com.
Visit us on the web www.jkmicro.com
Call 530-297-6073 Fax 530-297-6074
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66
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
here’s no deny-
ing that micro-
processor pipelines
are getting longer and
chips are getting faster. But honestly,
what good is a long pipeline? Does it
necessarily mean better performance,
cooler engineering, and bragging rights
at the next nerd party?
The high-end chips from Intel and
Advanced Micro Devices (not to
mention SPARC, PowerPC, and
Alpha (R.I.P.)) have pipelines that are
10 stages or longer, and most are
two-way superscalar and aggressive-
ly out of order. Some of these
aspects are actually purposeful fea-
tures (i.e., they’re beneficial in some
way), but others are hacks aimed at
overcoming inherent limitations in
the chip’s design.
PUT THAT IN YOUR PIPE AND
SMOKE IT
Somewhere along the line, a bright
spark in the marketing department
decided to coin the phrase “super-
pipelining.” Not to be outdone, one
of his colleagues came up with
“hyper-pipelining.” But these terms
don’t mean a thing. Pipelines are
pipelines, and no matter how long or
short they are, they all work in
essentially the same way. There’s no
magic length at which a pipeline
becomes an ultra-pipeline.
However, long pipelines can be
ultra-headaches for their designers. So,
as you learned in Part 1, long
pipelines are not always beneficial
even though they’re a necessary evil
needed to reach higher clock frequen-
cies. The more pipeline stages there
are, the more chainsaws you have to
juggle and the bigger the mess if
something slips up.
Just for fun, we’ll look at Intel’s
Itanium pipeline and the Opteron
from AMD. Both of these are high-
end, “super-pipelined” processors that
are about as complex as you can get
while still keeping your sanity.
As you can see in Figure 1,
Itanium’s pipeline is 10 stages long.
Even though the Itanium is an insane-
ly complex chip with 25 million tran-
sistors, it still has an in-order pipeline.
Athlon and other processors are out-
of-order machines that rearrange
instructions on the fly.
Itanium is so fast (800 MHz at first,
with faster chips sure to follow) that
fetching instructions requires three
pipeline stages (the five-stage proces-
sor did it in one). Itanium’s Stage 1
calculates the memory address of the
next instruction it needs to fetch.
Stage 2 accesses Itanium’s on-chip
instruction cache (one of three), and
Stage 3 puts the new instruction into
a buffer. At this point, there’s a break
in the pipeline while Itanium gathers
instructions into its small 24-instruc-
tion buffer.
After a brief stop in the buffer,
instructions move on to Stage 4 where
they are decoded and the chip decides
what type of execution unit (e.g., inte-
ger, floating point) it will use. Stage 5
performs register renaming, an
advanced technique that resolves the
difference between Itanium’s real reg-
isters and the registers the instruction
thinks it’s using. Note that Itanium
has so many registers, 256 in all, that
it takes two full pipe stages (6 and 7)
just to find and transfer operands from
them. Then, in Stage 8, Itanium actu-
ally executes the instruction, which
takes only one cycle. Stage 9 warms
Starting Down the Pipeline
t
Long pipelines are
needed to reach high-
er clock frequencies.
However, longer
pipelines aren’t nec-
essarily better in the
complicated world of
microprocessors. For
insight into the issue,
read Jim’s explana-
tion of the pros and
cons of processors
with long pipelines.
Jim Turley
FEATURE
ARTICLE
Part 2: The Long and Short of It
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
67
instructions to get the best perform-
ance out of 20-year-old code.
The Opteron’s 12-stage pipeline is
longer than Itanium’s because x86
instructions are more complicated and
harder to decode than Itanium’s com-
paratively organized VLIW instruc-
tions (see Figure 2). If you’re a pro-
grammer who has written x86 assem-
bler code, you know it’s not too diffi-
cult. But if you’ve ever had to disas-
semble x86 code, you know how
hideously complex that instruction
set can be. Imagine the Opteron doing
that disassembly in 1 ns (1 GHz).
The Opteron fetches three instruc-
tions at the same time, and almost
immediately converts them into its
own internal RISC notation. So, for
the first few pipeline stages, the
Opteron is a CISC processor; after
that, it’s purely a RISC machine. The
Opteron’s internal RISC instruction
set is proprietary to AMD and isn’t
documented anywhere.
The Opteron, like the Itanium, has
nine internal execution units for float-
ing-point instructions, integer instruc-
tions, branch instructions, etc. It tries
to keep as many of these nine units as
busy as possible by aggressive-
ly reorganizing and rearrang-
ing the instructions in its
queue. This means that x86
instructions can, and often
are, launched before other
instructions that appeared
earlier in the program.
Oftentimes, just a few parts of
an x86 instruction can be dis-
patched for execution because
a single instruction might
decompose into multiple
internal RISC operations, all
of which can be executed
independently.
The Opteron takes an
opportunistic approach to
reorganization. If one of its
up the data cache for a pending store
or handles last-minute branches.
Finally, Stage 10 writes the results of
the instruction into a register or to
memory (data cache, really). Whew!
ORDER OF EXECUTION
Itanium is pretty straightforward
compared to some of the more exotic
pipelines, but it still carries out some
out-of-order execution. Out-of-order
execution is just what it sounds like:
executing instructions in a different
order from the way they appear in the
program. Out-of-order execution dis-
obeys the programmer’s (or the com-
piler’s) sequence of instructions and
reorganizes them to make better use
of the chip’s hardware resources.
Certain high-end processors will
dispatch (begin processing) instruc-
tions out of order, while others will
only retire (finish processing) instruc-
tions out of order. Some processors
will do both. Itanium falls into the
middle category, launching instruc-
tions exactly the way they appear in
the code but not necessarily finishing
them that way.
For example, if the program calls for
one long, complicated instruction fol-
lowed by two short, easy instructions,
then Itanium can dispatch all three
simultaneously, assuming that the
integer and floating point execution
units aren’t busy. But there’s no point
holding up the two simple operations
just because the FP instruction is tak-
ing forever. Itanium allows them to
complete even though the
instruction before them isn’t
finished. This is in-order dis-
patch combined with out-of-
order retirement.
The exception to this rule is
if the three instructions are
somehow dependent on one
another. If the shift instruc-
tion is supposed to shift the
results of the floating point
square root, it cannot finish (or
even start) until the floating
point square root is done.
Itanium uses a register score-
board to detect this. Each of
the 256 registers has an invisi-
ble scoreboard bit that is auto-
matically set when an instruc-
tion is about to change the register in
some way. Other instructions are not
allowed to read from that register
until its scoreboard bit is cleared.
This simple expedient prevents
instructions from stepping on each
other’s results.
CISC PIPE COMPLICATIONS
Itanium is conservative by modern
standards when it comes to out-of-
order execution. On the other hand,
AMD’s upcoming Opteron is much
more aggressive about executing
instructions out of order. The two
processors should have roughly equiv-
alent performance, but they get there
in different ways.
The Opteron is an out-of-order
processor because it has to be. It exe-
cutes x86 instructions that are com-
patible with Athlon, Pentium, and
more than two decades of older x86
processors. Itanium, in contrast, exe-
cutes new IA-64 instructions that
explicitly define program parallelism
in such a way that the processor does-
n’t have to figure out anything. The
Opteron doesn’t have this advantage,
so it shuffles and reorganizes x86
1
2
3
4
5
6
7
8
9
10
Instruction queue
Gener
al
PC
Instr
uction
cache
Queue
instr
uction
Issue
instr
uction
Remap
registers
Access
registers
Access
registers
Ex
ecute
Data cache
Wr
ite bac
k
Figure 1—Intel’s Itanium pipeline is in order and 10 stages long.
L2
Instruction
cache
Con
v
e
rt
L1
Instruction
cache
Fetch
Decode
Decode
Decode
ALU
AG
U
ALU
AG
U
ALU
AG
U
ADD
MUL
Miscellaneous
Integer
buffer
Integer
buffer
Integer
buffer
FP
buffer
Figure 2—Advanced Micro Devices’s Opteron pipeline includes stages to
decode instructions and a different mix of execution units.
processor has two execution
units, it’s not a two-way
superscalar processor.
A more common exam-
ple is a dedicated address
generation unit (AGU). An
AGU is akin to a simpli-
fied general-purpose ALU
that’s tweaked for generat-
ing addresses. Usually, it is
able to add and subtract
but not multiply and
divide. An AGU often
treats carry and borrow dif-
ferently than a normal
ALU, depending on how
the processor likes to wrap addresses
around memory boundaries.
A load/store unit is another exam-
ple of a specialized execution unit,
which in this case is a chunk of hard-
ware dedicated to memory transfers.
With a separate load/store unit, a
processor can load operands from
memory while it also crunches num-
bers. This vastly improves bandwidth.
BROADLY PARALLEL THEMES
Apart from these special cases, truly
superscalar processors have an assort-
ment of execution units, usually with
some duplication. Itanium has nine
execution units: four integer units,
three branch units, and two floating-
point units. Coincidentally, AMD’s
Opteron processor has nine execution
units, although AMD chose a different
division of labor. In addition, the
Opteron has three integer units, three
address-generation units, and three
floating-point units like the Athlon
processor before it.
Do multiple execution units mean
multiple pipelines? Not really. Even
massively superscalar processors gen-
erally have only one pipeline in the
sense that all instructions pass
through the same five, 10, or 12
stages. The pipeline is wider because
multiple instructions are traveling
down the pipe at once.
In the cases of the Itanium, Athlon,
and Opteron, the chips fetch three
instructions simultaneously. (This is
coincidental, even though it’s affect-
ed by the nature of x86 code.) These
three instructions are cracked at the
same time, rearranged to fit internal
68
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CIRCUIT CELLAR
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nine execution units is free,
the Opteron will do its best
to find an instruction that
can use it and move it to
the head of the queue.
There are several tricks
involved in this process.
First, the Opteron must
make it look as though all
of the instructions ran in
order. It can’t arbitrarily
rewrite programs for you!
To do this, the Opteron
waits to commit the results
of most instructions. The
chip keeps hidden backup
copies of most registers and flags, and
it stores them permanently when the
instructions that should have come
before are finished. The more instruc-
tions the Opteron reorders, the more
shadow registers it has to juggle,
which adds a lot of hardware.
The Opteron also makes multiple
copies of the main x86 registers (for
example, AL, AX and SP). Each inter-
nal RISC operation thinks it’s using
the same registers, but in reality each
one has its own. The Opteron then
has the task of synchronizing all the
updates to these registers and resolv-
ing conflicts in the order they should
have occurred, not necessarily the
way they actually happened.
Resolving two or more branches at
once is even more exciting, but I’ll
save that for another day.
SUPER-DUPER SCALAR
In the midst of all this pipeline talk,
we breezed right over parallel, or
superscalar, execution. In one sense,
all microprocessors are parallel
because they perform multiple opera-
tions simultaneously. With a five-
stage pipe, five different instructions
are in various stages of completion.
But what’s usually meant by parallel
execution is superscalar execution,
which is the running of two or more
instructions through the same
pipeline stage at the same time. So,
superscalar execution is like a double-
barreled shotgun; it gives you twice
the bang for your buck.
Big superscalar computer systems
have been around for a long time, and
there are even some microprocessors
have been superscalar for years.
Today, superscalar execution is fairly
common and only low-end or mid-
range embedded processors tend to be
uniscalar (i.e., not superscalar).
Ideally, a two-way superscalar proces-
sor would be as fast as two separate
processors running at the same speed.
Realistically, however, this isn’t the
case. There are always drawbacks to
processing multiple instructions at
the same time inside the same chip.
It doesn’t take long to reach the point
of diminishing returns, which is why
the Opteron, Itanium, Alpha, and
other high-end processors all have
about six to nine execution units
instead of 100.
MASS EXECUTION
The first requirement of a super-
scalar processor is multiple execution
units. Recall that the execute stage is
one of the stages in a conventional
processor pipeline, usually located
somewhere in the second half of the
pipe. Unless you have two or more
execution units, there’s no point in
trying to execute more than one
instruction at a time.
Superscalar processors must have
multiple execution units. But just
because a processor has multiple exe-
cution units doesn’t mean it’s super-
scalar. Surprisingly, many uniscalar
processors have multiple execution
units. They might, for example, use
separate hardware circuits for multi-
plication and calculating square
roots. Any single instruction might
use one or the other, but never both
at the same time. Although the
Dispatch and register remapping
Branch unit
Integer unit
FP unit
Integer registers
(128)
FP registers
(128)
Predicate bits (64)
Figure 3—Intel’s Itanium includes twice as many integer units as the Opteron from
AMD. But, it’s at the cost of floating point execution.
www.circuitcellar.com
CIRCUIT CELLAR
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Issue 144 July 2002
69
buffers, and hopefully dispatched
simultaneously. This last stage, how-
ever, is the real key to maximizing
performance.
Itanium’s designers obviously
thought integer code was more impor-
tant (or at least more plentiful) than
floating-point code, so they put in
twice as many integer units as FP
units (see Figure 3). The designers of
the Athlon and Opteron balanced
these two fifty-fifty. Both camps dedi-
cated three units to branch resolution
and address generation, which indi-
cates the importance of branch han-
dling in a fast processor.
Superscalar processors can dispatch
an instruction only if an execution
unit is free to handle it. In Athlon’s
case, for example, only three integer
instructions (e.g., add, subtract, shift,
rotate, etc.) can be used simultane-
ously. If a fourth integer instruction
comes along, it has to wait in
Athlon’s internal instruction queue
until one of the other three finishes
and moves to the next pipeline stage.
Fortunately, that’s only a one-cycle
wait for Athlon (or most other RISC
chips). A worse case would be a cou-
ple of long-latency floating-point
instructions plodding their way
through Athlon’s two FPUs. If a third
floating point instruction comes along,
it would probably wait several cycles
before one of the FPUs is free again.
Obviously, the more execution
units a chip contains, the better its
chances of keeping additional instruc-
tions in flight at once. The flip side,
however, is complexity. The more
execution units a chip contains, the
more instructions it has to juggle and
the bigger the chip will grow. Also,
additional execution units don’t nec-
essarily help to move more instruc-
tions down the pipeline. You’re still
limited by what the programmer
wrote, and most programming lan-
guages (and most programmers) sim-
ply do not support parallelism.
SEARCHING FOR PARALLELS
You can’t squeeze blood from a
turnip, and you can’t extract paral-
lelism from a sequential program
(well, not much, anyway). Virtually
all of the software and PC programs
written today are inherently serial.
They’re designed in accordance with
Turing and von Neumann’s principles,
where one instruction follows another
in a straight line. Adding a million
execution units in parallel won’t help
when the program itself is sequential.
What’s the solution? The obvious
answer is to rewrite all your code
using parallel programming languages.
But that’s a bigger pill than most peo-
ple are willing to swallow. In the
meantime, companies like AMD and
IBM are extracting what little frag-
ments of instruction-level parallelism
(ILP) they can from existing software.
It isn’t easy and it isn’t pretty, but it
works and preserves existing software,
which is often the most important
consideration of all.
In contrast, Intel’s IA-64 family has
started down a different road. Itanium
uses VLIW concepts borrowed from
mainframes, minicomputers, and even
other microprocessors. Rather than
making the processor work hard to
reorganize and reshuffle instructions,
VLIW spells it out in software. The
chip actually can be pretty stupid
about how it dispatches and executes
instructions. Itanium makes no
attempt whatsoever to execute
instructions out of order or to look for
opportunities to rearrange instruc-
tions. In VLIW-land, that’s the compil-
er’s job and Itanium trusts what the
compiler tells it. VLIW is a lot like
RISC; it moves the problem out of the
hardware and into the software.
VLIW, which Intel calls EPIC, fires a
barrage of instructions at the proces-
sor. The chip then does what it’s told
without second-guessing the arrange-
ment of instructions or worrying
about dependencies between them. As
you can see, the software is smart,
and the hardware is dumb.
Theoretically, this allows Intel to
eliminate the complex rat’s nest of
dependency checking and out-of-order
hardware from the processor, which
makes the whole process simpler and
faster (Doesn’t this sound like RISC
all over again?). Thus, as Athlon,
Opteron, PowerPC G4, and others go
out of their way to shuffle and
rearrange instructions out of order,
Itanium does just the opposite.
SOURCES
Opteron processor
Advanced Micro Devices, Inc.
(408) 732-2400
www.amd.com
Itanium processor
Intel Corp.
(408) 765-8080
www.intel.com
Jim Turley is an independent analyst,
columnist, and speaker specializing in
microprocessors and semiconductor
intellectual property. He is the former
editor of
Microprocessor Report and
Embedded Processor Watch and host
of the annual
Microprocessor Forum
and
Embedded Processor Forum con-
ferences. You may write to him at
info@jimturley.com or visit his web
site at www.jimturley.com.
In a sense, Intel’s VLIW is a big
step backward. Early microprocessors
simply executed instructions one at
a time in program order. But years
ago, processor designers started reor-
ganizing instructions and executing
them out of order to take advantage
of little tweaks in the hardware that
the programmer might not know.
Today’s processors have taken that
concept of looking for the advantage
to the extreme. Now, Itanium moves
Intel’s processors back to the begin-
ning, executing exactly what the pro-
grammer (or compiler) has written.
Itanium retains the multiple execu-
tion units and the wide and fast
pipelines of other RISCs, but elimi-
nates the on-the-fly reorganization
that complicates those other chips.
The basic problem still remains,
though. How do you squeeze paral-
lelism out of a sequential program?
Currently, Itanium relies on its com-
pilers to discover small bits of paral-
lelism in normal C code (where there
isn’t much). Intel’s long-term goal
may be to encourage programmers to
shift to other languages where VLIW
(oops, EPIC) really pays off. Intel has
made a leap in hardware (forward or
backward, depending on your view)
and is betting that software can make
the big leap with it.
I
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Issue 144 July 2002
CIRCUIT CELLAR
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ave you ever
wondered if you’d
open the mythical
Pandora’s box? Because
of my curious nature, I’m prone to
act without full knowledge of what
I’m getting myself into. Although I
feel like I can relate to some aspects
of Confucian thought, I try to supple-
ment my curiosity with caution. I
start many projects without any
knowledge of what the outcome will
be. I’m not sure if I’m subconscious-
ly trying to set myself up for a fall,
or if I just need to constantly push
my own envelope.
This project, however, has given me
a new appreciation for the DOS FAT
file format. The tiny scraps of infor-
mation available on how it works are
a good indication of the black magic
originally used to create it. However,
it’s worth your while to try to make
sense out of this because it can be use-
ful for other projects. Therefore, most
of what I’ll describe here is applicable
to other devices that are based on the
same general DOS FAT file system.
In my previous column, I described
the parts of the DOS FAT file system
and how they are applied to the
SmartMedia to obtain compatibility.
You can refer to that overview for the
tables clarifying the information. Now
you’ll learn about the SmartMedia
module, and we’ll explore how the
DOS FAT file format is applied. In
addition, this project consists of cir-
cuitry, which interfaces a SmartMedia
socket with a host’s serial port. A
PIC18F452 handles the SmartMedia,
serial port, I
2
C storage, and power
selection. The serial command struc-
ture is kept simple, and it will afford
any computer or embedded system
“smart” access to a SmartMedia
device via a few simple commands.
C:
The DOS prompt is one of the most
recognizable messages known to com-
puter users. Although Windows has
almost succeeded with its plan to do
away with the DOS prompt, it still
can be found in many Start menus.
The letter in the DOS prompt is
usually an indication of the type of
physical apparatus connected as a
storage device. Even though any
device can have any drive letter, A
and B have become synonymous with
floppy drives, C and D with hard
drives, and E and F with CD drives.
In DOS, when a carriage return
(<cr>) is entered, an active device will
respond with its drive letter. This
indicates that the device is installed
and ready for use. For this project,
the processor will respond to a <cr>
with an S: designation after the
application has recognized that a
SmartMedia device has been inserted
into the SmartMedia socket and the
device has been identified. Prior to
that time, the application responds
with a “No Media” message or some
other error message.
One of the differences in the
PIC18xxxx series microprocessors is
the multi-level (high/low-level) inter-
rupt structure. The high-level inter-
rupt has fast in and fast out capabili-
ties, and can automatically save and
retrieve the most valuable registers.
In addition, it can interrupt program
flow (including a lower-level inter-
rupt) without requiring lengthy code,
decreasing the interrupt latency. Two
interrupts are used for the serial
interface. The command interpreter
routine and Character Received and
SmartMedia File Storage
h
Last
month,
Jeff
explained
how to
exchange embedded
data with your PC
applications. In Part 2,
he’ll cover the Smart-
Media module and
teach you how to nav-
igate within its DOS
FAT file structure.
Jeff Bachiochi
FROM THE
BENCH
Part 2: Directory Entries
www.circuitcellar.com
CIRCUIT CELLAR
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Issue 144 July 2002
71
One of the connections on the
SmartMedia interface is an output,
which reflects the device’s working
voltage. As you can see in Figure 1,
pin 17 (Vsense) of the SmartMedia is
connected to an input pin on the
processor via a pull-up. The
SmartMedia will pull the input to a
logic low if the module requires 5 V.
To handle both 3.3 and 5-V mod-
ules, this project was designed to run
entirely on either voltage. Doing so
allows the processor to be connected
directly to the SmartMedia, without
the need for voltage transition buffers.
When running on 3.3 V, the serial
interface will drop to a
±
6-V swing but
will still function well with most seri-
al interfaces. The application requires
a regulated 5 V. The 5 V along with an
on-board 3.3-V regulator is applied to
a Linear Technology LTC1470. Logic
Transmitter Empty interrupts handle
all the serial communications with
an external host.
The PIC18F452 has 1536 bytes (six
256-byte blocks) of RAM for tempo-
rary storage. Two of these blocks are
used as TX and RX ring buffers.
Commands from a host always
require an ending carriage return.
Characters received by this applica-
tion are placed into the RX buffer,
while characters placed in the TX
buffer by this application are sent out
to a host. When the command inter-
preter recognizes a <cr> in the RX
buffer, the interpreter searches the
buffer for a legal command. If the <cr>
is found by itself, the <cr> command
routine is evoked. Here’s where the
command prompt S:, or “no media”
message, is placed in the TX buffer for
transmission to the host. The message
is determined by the state of the
GFORMF (good format) flag bit. So,
determining the state of this flag is
where I’ll begin this month’s column.
INSERT MEDIA HERE
One of the most confusing aspects
of building or upgrading a PC is how
the working voltage of processors has
been reduced from a system’s 5-V
level down to 3.3-V (and lower) core
voltages. Getting those motherboard
jumpers correct for the processor you
were installing was a pain.
SmartMedia was developed at a time
when 5-V memory was the norm. The
first SmartMedia devices were 5-V
modules, now SmartMedia is 3.3 V.
Fortunately (or unfortunately) this
means that in order to be completely
compatible, you need to handle both
5- and 3.3-V devices.
Figure 1—The SmartMedia interface can run on either 5 or 3.3 V. The voltage is selected via ICZ. The RS-232 converter is not necessary when connected directly to the
TTL I/O of the host processor.
media and will let the applica-
tion know how much data can
be stored, how much data is
handled at a time, and how
many pages are grouped into a
block. Note that the block is
also the minimum cluster size
allocated for files.
MODULE CIS/IDI
Now that you know the
physical makeup of this partic-
ular module, you can access
the memory looking for the
Card Information Structure
(CIS) and Identify Drive
Information (IDI). This information
must be located on the first good sec-
tor of the media. Finding the CIS/IDI
indicates that the media has been
physically formatted and can be recog-
nized as a PC-ATA card (when insert-
ed into a PCMCIA ATA adapter). All
pages have been checked beforehand
and whole blocks marked as bad if all
the pages are not error free.
The CIS assures that you can expect
to find SmartMedia-specific informa-
tion at the appropriate locations (i.e.,
the block good/bad indicator or page
checksum). Comparing data on the
CIS page to that stored in the applica-
tion’s CIS table identifies a good CIS.
At this point, what you have is simi-
lar to a blank diskette. You know
what it is and how much it could
hold, but not how it does it.
MODULE BOOT SECTOR
The operating system determines
how data will be stored. Like other
non-compatibility issues, the storage
format used by the OS is not necessar-
ily compatible with other OSs and
may not be readable on machines
running other OSs. So, you must
determine how and where the media
is to be used in order to ensure com-
patibility. This project assumes that
the SmartMedia will be used with the
Windows/MSDOS-compatible OS, and
so the SmartMedia will have the DOS
FAT file system format.
The physical organization of all
disks is in the form of cylinders,
heads, and sectors (CHS). The drive
contains multiple magnetic surfaces
of floppy/hard platter(s), which are
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Issue 144 July 2002
CIRCUIT CELLAR
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inputs to the ’1470 select one
(and only one) of the two input
voltages and apply it to power
the rest of the circuitry.
A mechanical switch on the
SmartMedia socket indicates to
the processor that a SmartMedia
module has been inserted into
the socket. Upon power-up, the
application must initialize its
I/O ports and peripherals, and
place the SmartMedia socket
interface into a safe condition
before checking the SmartMedia
socket for module insertion. I
chose to use input port C.2 on
the microprocessor as the insertion
input because it can produce an inter-
rupt on an edge transition. Although it
isn’t of any particular importance that
an insertion be detected and acted on
quickly, it would be prudent to disable
(and ensure the safety of) the
SmartMedia socket interface as soon
as the module is removed from the
socket. Therefore, the media is
removed immediately and independ-
ently of the main execution loop.
When media insertion is detected,
the application checks for the proper
working voltage and, if necessary, it
instructs the LTC1470 to remove the
3.3 V and apply 5 V as the circuitry
source. After the working voltage has
been set, a little investigative work can
be done to identify the inserted module.
MODULE ID
The application’s first access to the
SmartMedia is to its ID register. A
device ID read will produce a manu-
facturer’s code data byte and a device
data code byte. The general format
of communications with the
SmartMedia module can be found in
Figures 2, 3, and 4.
SmartMedia communication is sim-
ilar to I/O peripherals on a multi-
plexed data bus. Commands, address-
ing, and data values are passed using
the write enable strobe (WE) for infor-
mation going to the module, and the
read enable strobe (RE) for information
coming from the module. The module
recognizes commands when the com-
mand latch enable (CLE) is held high
by the application during communica-
tions. The module recognizes an
address (LSB first) when the address
latch enable (ALE) is held high during
communications. Additional commu-
nication (without CLE or ALE) indi-
cates data being passed. Although the
SmartMedia module has a status regis-
ter that can be read, a separate
ready/*busy output from the module
can be used to determine when
the module is busy doing inter-
nal processing (i.e., updating
address pointers or erasing/pro-
gramming a block of data).
The data returned by the ID
read command is used as an
offset in the DEVICE_CODE
table of your application. This
table provides CAPACITY (in
megabits), UNITS_PAGE
(unit = 256 bytes), SECTORS_
BLOCK (pages/block), and
NUM_BLOCKS (total blocks =
NUM_BLOCKS × 0x100).
These values are the physical
parameters of the inserted
Figure 3—Similar to the read format, the write format allows data
to be written into the SmartMedia.
Figure 2—Look at the general format for reading data from the SmartMedia.
Write
command
Write
address
Read
data
CE
CLE
ALE
*WE
*RE
*BSY
I/O
Command
Multiple
address
bytes
Multiple
Data
bytes
Write
command
Write
address
Write
data
*CE
CLE
ALE
*WE
*RE
*BSY
I/O
Command
Multiple
address
bytes
Multiple
data
bytes
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CIRCUIT CELLAR
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Issue 144 July 2002
73
read by one magnetic head per sur-
face. Each surface is divided into
individual rings, or tracks, that pass
beneath the head as the surface
rotates. Each head can be positioned
over any track on its surface. Each
track is divided into a number of
segments, or sectors, which hold one
unit of data bytes. Hence, each sec-
tor on the drive can be identified by
its CHS position.
When you’re talking about the stor-
age area, it’s much easier to think of
this as one linear chunk rather than
individual sectors of cylinders of heads.
Therefore, Logical Block Addressing
(LBA) is used to translate the CH (of
CHS) into linear LBA. Remember the
UNITS_PAGE and SECTORS_BLOCK
identified earlier? The block size is
important here because the physical
format of SmartMedia also uses
Block Addressing, or Physical Block
Addressing (PBA) to be more specific.
You should note that this is extreme-
ly important because the relationship
between PBA and LBA can be a cause
of great confusion.
The first thing found on any
disk/diskette formatted for DOS will
be the boot sector. The boot sector
is found in the first sector of the
disk, where PBA/LBA = 0. You
already know that the CIS/ISI
should be in the first good sector of
the first good PBA. However, if this
is a bad block, you may need to go
the next PBA to find it. So, do we
have a conflict with the location for
the boot selector? Well, yes and no.
If we define a relationship between
LBA and PBA as something other
than equal, we can make everyone
happy (if not confused).
By placing the boot sector in the
SmartMedia at the next good sector
of the next good PBA, we have
established a relationship for this
module between PBA and LBA. On
SmartMedia with no defective sectors
the LBA would have an offset of 1
from the PBA. You would need to
look at the PBA+1 to find the LBA = 1.
For SmartMedia with some bad ini-
tial blocks, this offset would be
greater than 1. The LBA is written
into the Block Address Field (BAF) in
the redundant area of each Sector or
Page within the same PBA. This
means that you can search for a spe-
cific LBA of interest and that the
PBA is independent of the LBA (i.e.,
an LBA can be moved to a different
PBA without affecting the rest of the
file structure). You’ll realize the
importance of this when I discuss
the saving of files.
The boot sector can actually con-
tain executable code; however, I
won’t cover that topic here. Instead,
you need to verify that the boot sec-
tor exists and retrieve some addi-
tional information from it. Each sec-
tor, or page, of data is separated into
three areas: even, odd, and redun-
dant. Separate commands can be
used to retrieve area data from a
page. Each command begins access
to a page in a specific area of stor-
age. The application may read any or
all of the data area. In fact, continu-
ously reading data will retrieve data
from the following areas and on into
the next page.
Three RAM sections are set aside
for the even (256 bytes), odd
(256 bytes), and redundant (16 bytes)
areas so that a full page can be stored
at one time. With the boot sector read
from the SmartMedia into RAM, the
application looks for the fixed data
signature 0xAA55 in the last data
bytes of the odd page at sector bytes
0x1FFE–0x1FFF. This identifies the
boot sector and acknowledges the
presence of some additional informa-
tion. The boot sector indicates where
to look for the next part of the DOS
format, the partition sector.
The boot sector has space allocated
for four partitions. Usually, only
hard disks use multiple partitions
and the SmartMedia will be interest-
ed in only the first partition sector
information. The boot sector carries
two pieces of information for each
partition, the partition start and end
address in CHS format and partition
sector and partition size in absolute
sectors. As I’ve indicated, the boot
sector has been arbitrarily named
LBA = 0. Use the partition sector
entry in the boot sector to locate the
partition sector information. For an
8-MB module this is logical sector
0x19 (LB1-PAGE9).
LBA-PBA TRANSLATION
So far, you haven’t run into any
problems finding the CIS-IDI and
boot sector (except for potential bad
sectors forcing a move to the next
physical block). The terminology can
be confusing at times, so I’ll bring
you up to speed.
Sectors are grouped into physical
blocks of 16 512-byte pages (in the
case of an 8-MB module) and charac-
terize the physical makeup of the
SmartMedia. In this case, each physi-
cal block is made up of 16 physical
sectors. Physical block 0 consists of
physical sectors with a PBA of 0x0-F.
Physical block 1 consists of physical
sectors with a PBA of 0x10-1F. You
can see how the pattern goes.
The logical makeup of the DOS FAT
file system is that of logical sectors
grouped into logical sectors, cylin-
ders, and heads (these were just
defined by the boot sector). You’ll see
shortly that the size of a sector is also
512 bytes, which is the same as a
physical page not counting the redun-
dant area. Each logical sector has an
LBA. Because the logical sectors/track
equals the physical sectors/block, a
logical block is identical to that of a
physical block, 16 logical sectors.
Logical block 0 holds logical sectors
with an LBA of 0–0xF, while logical
block 1 holds logical sectors with an
LBA of 0x10–0x1F.
This all works to make the LBA
relate directly to the PBA because
they’re equal in size. The offset differ-
ence between the boot sector LBA = 0
and PBA = 0 is the key to finding the
rest of the logical blocks and sectors.
As I explained earlier, each logical
Write
command
Programming
*CE
CLE
ALE
*WE
*RE
*BSY
I/O
Write
Figure 4—After the data is written to the SmartMedia,
a programming command initiates self-programming
of a block of data.
MODULE PARTITION SECTOR
The partition sector is the second
part of the DOS FAT file system and
defines all of the remaining unknowns.
To locate the partition sector, you
must look to the LB/PB conversion
table for the location of logical block
(LB) 1 (LBA = 0x19, sector 9 of LB 1
according to the boot sector informa-
tion for an 8-MB SmartMedia module).
The addresses (1 × 2) and (1 × 2) + 1 of
the EEPROM device are read to deter-
mine the physical block (PB) in which
the partition sector (sector 9) will be
located, PBA = (PB × 16 sectors per
block) + sector offset 9.
With the partition sector read from
the SmartMedia into RAM, the appli-
cation looks for the fixed data signa-
ture 0xAA55 in the last data bytes of
the odd page at sector bytes
0x1FFE–1FFF. This identifies the parti-
tion sector and acknowledges the pres-
ence of some additional information.
In the partition sector, the applica-
tion can retrieve logical format infor-
mation like the number of bytes per
sector (equals the physical bytes per
74
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
far) would require 16 KB of storage
(8192 blocks × 2 bytes per block).
That’s a job for external EEPROM.
I chose to use an I
2
C serial EEP-
ROM for this LB/PB conversion table
because it’s available in large densi-
ties. The PIC has I
2
C support making
the interface and software routines an
easy addition to the circuit.
Initialization should clear the EEP-
ROM device each time a SmartMedia
module is inserted and recognized to
ensure that the table is free from
extraneous data. Then the redundant
area of each physical block can be
read from the SmartMedia and legal
(used) logical blocks can have their
physical block number stored in the
conversion table’s logical block
address in the E
2
. The physical block
number (a 16-bit value) is stored in
consecutive addresses in EEPROM at
addresses (logical block number × 2)
and (logical block number × 2) + 1. To
keep this table up to date, the physi-
cal block numbers must be updated
whenever a write changes
SmartMedia data.
block’s number is written into the
physical block where it resides in
the SmartMedia module, begin-
ning with the boot sector’s logical
block 0. That’s important because
when the SmartMedia needs to
rewrite any sectors/blocks to new
physical locations, these will
retain the LBA but get a new PBA.
Only the physical location of the
block changes; it retains its logi-
cal relationship.
So, if the application needs to
find a particular LBA, it has two
choices. It can either read physi-
cal blocks until it finds the logical
block number it is interested in,
or it can make a table of used log-
ical blocks in order to find where
a logical block is physically locat-
ed. Clearly, if the table is kept up
to date, it’s the quickest way to
locate a PBA. However, this
requires building a table and keep-
ing it somewhere. Although the
PIC18F452 has over 1500 bytes of
RAM, a table of all LBAs for the
largest SmartMedia available (so
sector of the SmartMedia) and the
number of sectors per cluster, which
equals the physical sectors per block
of the SmartMedia. Although these
values are not required to match, hav-
ing them correspond makes conver-
sion much more simple. The media’s
ID and label are found in the partition
sector. Information about the final
two parts of DOS FAT file system can
be found in the FAT and directory.
The FAT type is identified, as well as
how many FAT tables are used and
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
75
how much room they require. The
partition sector also indicates the
maximum number of entries the
directory will contain.
The FAT is located in the LBA sec-
tor following the partition sector. In
the example of an 8-MB SmartMedia
module, the FAT1 table will begin in
LBA 0x1A because the LBA of the
partition sector is 0x19. According to
the data in the partition sector, there
are two FATs that are each three sec-
tors in length. This means that FAT2
will begin in LBA 0x1D (FAT1 + three
sectors). The directory begins in the
LBA following the last sector used by
the last FAT table. This would put
the beginning of the directory in LBA
0x20 (FAT2 + three sectors).
MODULE DIRECTORY TABLE
The directory is the third part of
the DOS FAT file system. From the
partition sector you learned that the
directory table could have up to
256 entries. Each directory entry (file
or subdirectory) requires 32 bytes of
table space, and one sector will hold
16 entries. Thus, a maximum of
256 entries will require a directory
table of 16 sectors (256/16).
Initially, the directory table doesn’t
have an entry and will contain all
zeros. If you’re searching the directo-
ry for an entry and the first value is
zero, then you can rest assured that
this is an empty entry. Directory
table entries that are in use contain a
printable ASCII character (actually a
slightly abbreviated set). When an
entry is deleted, only the first charac-
Listing 1—The DIR command reports to the host via the serial port.
S:
DIR
Volume in drive S is
Volume Serial Number is 0000-0000
Directory of S:
IM01OLYM
0000 files(s) 0000000000 bytes
0001 dir(s) 00008E0000 bytes free
S:
76
Issue 144 July 2002
CIRCUIT CELLAR
®
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ter is changed (to an 0xE5). Therefore,
some files can be undeleted because
they’re still present if the clusters
holding the file haven’t been reused.
When a real entry is found, the
application can determine whether
it’s a file or subdirectory entry by
looking at the file size (the last four
bytes in the entry). The attribute bit 4
is set for subdirectory entries by look-
ing at the entry’s attribute byte. You
can refer to last month’s tables to see
what else is in the directory entry.
The word value stored at offset
0x1A–1B is a cluster number and indi-
cates where you will find either the
beginning of the file or the subdirecto-
ry. Remember that the partition sector
told you the cluster size, which is
equivalent to the block size. This
means that any file or subdirectory
requires a minimum of one cluster of
storage space (even if it’s only 1 byte
long). In addition, if a file is larger than
one cluster, it must allocate additional
space, whole clusters at a time.
So, from the directory entry you
can tell where a file starts. But what
about large files that require more
than one cluster, where are the addi-
tional clusters? The FAT indicates
how the clusters are chained together.
As far as subdirectories go, a subdi-
rectory entry points out to the cluster
where a new set of directory entries
can be found. When a new subdirecto-
ry is created, two entries are placed
into it, the “.” and “..” entries. These
are pointers to the sub- and parent
directory and they help navigate the
directory structure. I’m going to skip
over the topic of long file names
here, but be aware that long file
names bend the rules of the directory
entry in order to fit into the 32-byte
directory entry format.
MODULE FAT TABLE
Back in the partition sector you
found an indication of the FAT type.
FAT12 is the most common for small
storage devices. The “12” indicates
the number of bits used to hold a
cluster number. A maximum of 4096
clusters (actually, this number is lim-
ited to the range of two and 4086)
would be possible. You can see from
this number that you quickly run
into trouble (huge cluster sizes) with
larger storage media. That’s why you’ll
find FAT16 and FAT32 file systems.
It’s a pain working with a byte and a
half, especially when the 12-bit values
are packed together. Originally, this
was done to save one sector per FAT.
Although it’s clever, it creates more
work to pull apart the packed 12-bit
values. Two 12-bit values are packed
into three bytes using an unusual
arrangement, even byte b7-b0, odd
byte b3-b0, even byte b11-b8, and odd
byte b11-b4. Sixteen- and 32-bit FAT
are nice whole bytes and don’t require
fancy packing and unpacking.
In terms of code, if you read a
word starting with the first byte of a
12-bit packed 3-byte entry in LSB-to-
MSB format and OR it with 0x0FFF,
you have the cluster number for the
even-numbered FAT entry. And if
you read in a word starting with the
second byte of a 12-bit packed 3-byte
entry in LSB-to-MSB format and
rotate it right four times (with zeros
coming into the most significant bit),
you have the cluster number for the
odd-numbered entry.
The first two clusters, zero and one,
are reserved. The FAT entry for these
clusters must be initialized to 0xFF8
and 0xFFF (that’s 0xF8, 0xFF, and 0xFF
as packed data). This is why the maxi-
mum possible cluster number is
slightly less. A few values in the FAT
table are reserved. An entry of zero
means the cluster isn’t used, one is
illegal, and 0xFF7 indicates a bad clus-
ter. Any entry that’s higher means last
cluster (EOF). DOS uses the FAT to
determine where it can store new data
in an unused cluster.
A cluster defined in the directory
entry, pointing to the beginning clus-
ter for a directory entry, also refers to
a cluster entry in the FAT. Let’s say
the directory entry for a file points to
cluster two. You can find the begin-
ning of that file in cluster two and an
indicator in the FAT for cluster two of
the status of that cluster. If the 12-bit
value stored in the cluster two entry
of the FAT is 0xFF8 or higher, then the
file ends within cluster two. However,
if the FAT entry for cluster two has
another value (e.g., 2–0xFF6), then this
value is the next cluster number in
the file’s chain.
Read this cluster for more file data
and then refer to the FAT entry for
that cluster number to see whether
the file continues in additional clus-
ters or ends there. You can, of course,
use the size value in the directory
table to determine how many clusters
there should be and how many bytes
of the last cluster are actually used.
Listing 2—The CD dirname command reports to the host via the serial port.
S:
CD IM01OLYM
S:/IM01OLYM
DIR
Volume in drive S is
Volume Serial Number is 0000-0000
Directory of S:/IM01OLYM
.
..
P1010001.JPG 0003034D bytes
P1010002.JPG 00030330 bytes
0002 files(s) 000007077D bytes
0002 dir(s) 0000861A83 bytes free
S:/IM01OLYM
CD ..
S:
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
77
SOURCES
LTC1470 Switch
Linear Technology Corp.
(408) 432-1900
www.linear.com
PIC18F452 Microcontroller
Microchip Technology Inc.
(480) 792-7200
www.microchip.com
Olympus digital camera
Olympus America, Inc.
(800) 645-8160
www.olympusamerica.com
SSFDC Forum
www.ssfdc.or.jp/english/index.htm
Jeff Bachiochi (pronounced BAH-key-
AH-key) is an electrical engineer on
Circuit Cellar’s engineering staff. His
background includes product design
and manufacturing. He may be
reached at jeff.bachiochi@circuitcel-
lar.com.
You know how a file or subdirecto-
ry entry points to a cluster. But, how
is a cluster number related to the log-
ical blocks (LB) of the DOS FAT file
system? Clusters zero and one are
reserved, and the first usable FAT
entry is two, cluster two. Therefore,
cluster two will refer to the first stor-
age cluster, which is the one that fol-
lows the root directory.
You know the root directory begins
in LB = 2, specifically LBA = 0x20,
and has 256 16-byte entries for a table
length of 10 sectors. That puts the
first available storage at LBA = 0x30.
LBA = 0x30 is the first sector of LB =
3, whereas cluster two must refer to
LB = 3. In this case, + 1 is the cluster
offset and one is added to the cluster
number to get the LB = 3. This means
that the 16 sectors in that LB will be
LBA = 0x30–0x3F.
ACCESSING THE DIRECTORY
The DIR command is necessary to
make use of the DOS FAT file sys-
tem. The DIR command will access
the present (initially the root) directo-
ry and produce information about the
storage media and files, or subdirec-
tory entries, located within the
directory table. When this applica-
tion’s command interpreter recog-
nizes the DIR command, it jumps
into a routine that emulates the
standard DIR command. This is done
through six routines that report its
findings, volume, serial, directory,
file_bytes, and free_bytes.
The first two reports are the volume
name and serial number. The 11-char-
acter volume name and double word
serial number were originally read
from the partition sector and stored in
RAM when the module was inserted.
These items may or may not have been
initialized with any useful information.
Many normally skip this option when
storage media is formatted.
The third routine takes the present,
or working, directory LBA and con-
verts it into a PBA. This sector is read
from the SmartMedia and the applica-
tion scans directory entries looking
for legal ones. Only the first character
of each 32-byte entry needs to be
checked. Erased entries are skipped,
and an empty entry indicates that
there are no additional entries. In this
case, the partition table defined a
maximum of 256 entries (that’s a full
block of 512-byte sectors).
If a legal entry is found, the appli-
cation extracts the FILE_NAME1-8,
FILE_EXT1-3, cluster number, and
FILE_SIZE from the directory entry.
Given that bit 4 of the attribute byte
indicates whether the entry is a file
or subdirectory, the application can
perform separate tasks. If this is a
file, then the FILES counter is incre-
mented and the file size is added to
a USEDBYTES accumulator. The
application then reports the
FILE_NAME, FILE_EXT, and
FILE_SIZE. If this is a subdirectory,
then the DIR’s counter is increment-
ed and the application reports the
FILE_NAME (directory name).
The final two routines are file_bytes
and free_bytes. File_bytes reports the
total number of files found (in this
directory) and the total number of file
bytes used. Free_bytes reports the
total number of subdirectories found
(in this directory) and the number of
bytes free for use. This routine finish-
es with a report of the command
prompt. Take a look at Listing 1 for a
display of the DIR command report to
the host via the serial port.
SUBDIRECTORY ENTRY
Even though I’ve used this
SmartMedia in my Olympus Digital
Camera, there are no files shown on
this SmartMedia because the camera
puts its picture files into a subdirec-
tory. Therefore, I’ve got to be able to
change directories to see them. A
CD dirname command must be rec-
ognized. This differs slightly from a
DIR command in that I don’t have
to report anything other than suc-
cess or failure, and so the directory’s
entries must be searched again. But
this time when an entry is found it’s
compared to the dirname given in
the CD request.
If a match is found, the cluster num-
ber in the entry is saved as the new
LSA_DIR. This is the variable used as
the pointer to the present directory.
The next time a DIR is requested,
this LSA will be converted to a PBA
and read from the SmartMedia. In
addition, the dirname is added to the
drive designation and the new com-
mand prompt is reported. When a
match is not found an error message
is reported. The directory pointer
LSA_DIR remains unchanged.
If a dirname of “..” is used while in
a subdirectory, the search will find a
match. This can be seen in the direc-
tory list of a subdirectory. The “.”
subdirectory entry points to itself,
while the “..” subdirectory entry
points back to the parent directory.
To simplify this application, only one
subdirectory level is saved with the
drive designation. Take a look at
Listing 2 for a display of the CD
dirname command report to the host
via the serial port.
NAVIGATION COMPLETE
Now that you can maneuver within
the SmartMedia’s DOS FAT file struc-
ture, you can begin working with
files. Whew! No wonder you don’t see
much published on this. From now
on when I think DOS FAT, I’ll think
COW (can of worms). Next month
bring your tackle box.
I
78
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
he latest Circuit
Cellar
reader sur-
vey is complete and,
as usual, has some
interesting nuggets of information.
Unlike supply-side driven market
research (e.g., quarterly shipments),
the Circuit Cellar survey provides
useful insight into what designers in
the trenches are thinking.
In some cases the survey results
reinforce conventional wisdom. For
instance, when was the last time you,
or for that matter, anyone you know,
designed in a 4-bit chip? It’s lonely at
the bottom of the processor pecking
order with only 6% of survey respon-
dents signing on the 4-bit dotted line
(see Figure 1). A likely explanation
for the weak support for 4-bit chips
is found in the overwhelming popu-
larity for 8-bit parts. A full two-
thirds (67%) of respondents signed-
up. Why bother messing with some
obscure mini-me 4-bit chip when
entry-level mainstream 8-bit parts
can do more for less?
The 32-bit chips needed to carry the
ever-bulkier software baggage fared
pretty well, too. One-quarter (26%) of
survey respondents showed interest,
proving that the long-awaited (and
long-hyped) migration to 32-bit chips
is slowly but surely underway.
If there’s any surprise with the
results, it’s the significant showing
(42%) for 16-bit chips. The result is
interesting, because 16-bit parts have
always been dark horses, seemingly
relegated to combine the worst of both
the 8- (limited performance and mem-
ory) and 32-bit (cost, power, size)
worlds. But, far be it from me to impose
my opinion over the collective wis-
dom of survey respondents. Designers
are saying 16-bit parts have a place in
their quiver of silicon solutions. And
judging by the raft of releases crowd-
ing my in-basket, suppliers are saying,
“You want it, you got it.”
SWEET (AND SMALL) SIXTEEN
Much as when working with 8-bit,
where seminal architectures such as
the ’51, ’68, and PIC still prevail,
designers can go back in time to find
answers to their 16-bit questions. A
case in point is the Texas Instruments
MSP430 family of 16-bit MCUs. In one
of my earlier articles (“Sweet Sixteen,”
Circuit Cellar
126), I traced the roots of
the MSP430 all the way back to chips
that served as the basis for TI’s venture
into personal computers in the ’70s.
Again, as with 8-bit parts, the popu-
larity of yesteryear’s parts is explained
by the realities of the embedded mar-
ketplace. Designers want the lowest
price, lowest power, simplest chip that
can meet their goals and hold all of
the newfangled trimmings. With it’s
multiple addressing modes and memo-
ry-to-memory architecture, the
MPP430 may not be a theologically
pure RISC. But, putting the emphasis
on the “R,” it’s a fact that in the old
days, all chips were reduced as a mat-
ter of necessity.
Eight Isn’t Enough
t
Tom Cantrell
Figure 1—Interestingly, I was surprised to see that 16-
bit chips garnered a better than respectable showing in
the latest Circuit Cellar reader survey.
Noting the
fact that
67% of
respon-
dents in a
Circuit Cellar reader’s
poll had a proclivity
for 8-bit chips, Tom’s
asking you to forget
about bits for a
moment and examine
alternatives from TI,
Cyan, and Adelante.
SILICON
UPDATE
6
67
42
26
28
35
55
58
4-bit
MCU/M
PU
8-bit
M
CU/M
PU
16-bit
M
CU/MP
U
32-bit-
plus
M
CU/M
PU
DSP
PLD/FPGA
SRAM,DRAM
EEPR
OM,
Flash m
em
or
y
100
90
80
70
60
50
40
30
20
10
0
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
79
at the maximum 25-MHz clock rate,
depending on the instruction mix and
more so the cache-hit ratio. That’s a
lot faster than the 1- to 2-MIPs 8-bit
chips of the good-old days, but the lat-
est 8-bit chips are pushing double-
digit MIPs ratings as well. Although I
don’t have the spec sheet, the nominal
clock rate, watch crystal clock genera-
tor, multiple clock domains, and
hand-held (i.e., battery-powered) target
markets all imply the prospect of low-
power consumption.
Despite the apparent (and welcome)
lack of press release pretension, even
the sparse eCOG1 data at hand piques
my interest. For instance, the chip
includes a 512-line instruction cache
that works in conjunction with direct
connect external SDRAM. Reflecting
the real time requirements of embed-
ded apps, the cache has what’s called
Deterministic mode (a fancy name for
turning it into RAM), and individual
cache lines can be locked. Both the
cache and SDRAM interface are some-
thing you’d more likely find on a 32-
bit processor than on an 8- or
16-bit controller.
There’s also an External
Host Interface (EHI), which
provides a 16- or 32-bit DMA
interface to an external host.
The DMA controller sup-
ports circular and linked-list
schemes to minimize the
Two new members of the ’430 fami-
ly, the ’11x2 and ’12x2, remind that
more bits do not necessarily make a
bloated chip. In fact, except for the
16-bit instruction set and ALU, a
close look reveals these parts are oth-
erwise similar to their lean and mean
8-bit counterparts (see Figure 2). The
chips are certainly like 8-bit parts in
their memory and I/O pretensions.
Four to 8 KB of flash memory for
code, an extra 256 bytes for data, and
256 bytes of RAM is a more likely
home for ASM rather than C or Java.
As an aside, I should note that the
flash memory retention time guaran-
tee is 100 years. It’s clear that TI has a
handle on the concern over flash
memory chip senility posed by other
vendors’ meager 10-year guarantees.
What could be more blue collar
than the collection of I/O: a 16-bit
timer, 10-bit A/D converter, USART,
and so on? The MSP430 does have
some modern tweaks, for example, a
fast autoscan mode and data transfer
controller for the 200-ksps A/D con-
verter. Nevertheless, it’s pretty clear
that when it comes to peripherals,
having more bits in the CPU doesn’t
mean less mainstream I/O.
What about power consumption? I
suppose it’s no surprise that, all else
(except the ALU) being equal, the
MSP430 family would be competitive,
but in fact the TI parts even put many
8-bit parts to shame. Operating across
a 1.8- to 3.6-V range, the 16-bit chips
consume a mere 200 µA per mega-
hertz. With a CPI approaching one,
we’re talking a fraction of a milliwatt
per MIPS. Better yet, cut power con-
sumption to nanoamps with Standby
mode, which is easy to use because
TI, paying attention to the details,
designed the chip to wake-up and get
going again in just 6 µs.
Historically, the mainstream
embedded prospects for 16-bit chips
like the 68K and ’186 were
limited to applications with
relatively high pin counts. By
contrast, the MSP430 parts
match their 8-bit I/O and
power consumption aspira-
tions with small 20- (’11x2)
and 28- (’12x2) pin packages.
And when I say small, I’m not
just talking about pin count. Thanks
to the low power and small die size,
these plastic small-outline packages
get a chance to live up to their name
with the tiniest versions barely more
than a 0.25
″
(6.6 mm) on each side.
Regarding price, these 16-bit parts
may not match the loss-leader 8-bit
chips, but at less than $3 in volume
(10K) they come mighty darn close.
Considering the extra performance
and features, the 16-bit price differ-
ence is arguably a NOP for many
embedded applications. Even the tools
are a bargain more befitting an 8-bit
chip. There’s certainly no 16-bit stick-
er shock for the MSP-FET430P120,
which costs just $99 (see Photo 1).
NEW CHIP ON THE BLOCK
There’s further evidence that 16-bit
devices are more than a fill-in-the-gap
fad. The introduction of new architec-
tures from new suppliers is always a
sign of market interest. The eCOG1
from Cyan Technology is a good exam-
ple (see Figure 3). Keeping in mind I
have only a few pages of preliminary
data from Cyan, there’s little obvious
difference between the eCOG1 and
other high-end 8-bit MCUs. A decent
amount of memory (64 KB of flash
memory and 4 KB of RAM), a full
bank of I/O (including a 12-bit ADC),
copious timers and serial ports, and
even a temperature sensor are neat,
but nothing you won’t find on the lat-
est high-integration 8-bit parts.
Meanwhile, the programmer’s model
looks like a 6502 on steroids (see
Figure 4). It has an accumulator and a
couple of index registers, all stretched
to get beyond 64 KB in a pinch. Of
course, there are popular 8-bit chips
like the Z180 and 68HC12 that have
taken a similar beyond 64-KB tack.
The performance of the eCOG1 is
good, but not outlandish. I’d say
you’re looking at roughly 5 to 10 MIPs
Test
V
CC
P2.5/R
OSC
V
SS
XOUT
XIN
*RST/NMI
P2.0/ACLK/A0
P2.1/INCLK/A1
P2.2/TA0/A2
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/V
REF+
P2.3/TA1/A3/V
REF–
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Test
V
CC
P2.5/R
OSC
V
SS
XOUT
XIN
*RST/NMI
P2.0/ACLK/A0
P2.1/INCLK/A1
P2.2/TA0/A2
P3.0/STE0/A5
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/V
REF+
P2.3/TA1/A3/V
REF–
P3.7/A7
P3.6/A6
P3.5/URXD0
P3.4/UTXD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MSP430
x
11
x
2
MSP430
x
12
x
2
Figure 2—The MSP430F11x2 and ’12x2 from TI may
be 16 bits under the hood, but their size, power con-
sumption, and price are more like an 8-bit chip.
Photo 1—Low-cost tools are a hallmark of 8-bit chips that Texas Instruments
carries forward with the 16-bit MSP430 family.
nearly 10 years in a variety of applica-
tions, such as pagers, gas meters, and
automated toll collection systems.
Notably, that means there’s no wait-
ing around for tools and such. The
company offers a $249 eval board (see
Photo 2) that uses the chip’s built-in
eICE debug interface and includes
such extras as 8 MB of SDRAM and
10/100 Ethernet. There’s also a C tool-
chain noteworthy for being fully vali-
dated against ANSI/ISO conformance
tests, all the more impressive consid-
ering it’s free.
THE LONG AND SHORT OF IT
Another interesting import comes
from Belgium-based Adelante
Technologies. As the result of a merg-
er between the Philips DSP division
and Frontier Design (the latter itself a
spin-off from the Mentor Graphics
80
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
software overhead typically associated
with buffer management.
Even more unique is what’s called
the IntAct communications interface,
licensed from an outfit called Amino
Communications. After visiting Cyan’s
and Amino’s web sites, I was able to
glean that IntAct is a kind of propri-
etary econo-version of high-perform-
ance serial I/O schemes like Rapid I/O
or Infiniband. In essence, the IntAct
port is like a router with backbone
and local upstream and downstream
links. Nodes connected to local links
can establish a virtual circuit connec-
tion across the backbone similarly to
the way TCP/IP allows computers to
connect via the Internet. With a
clock and two data lines in each
(upstream and downstream) direction,
the spec mentions a typical data rate
of 180 Mbps. It’s not the gigabit-plus
of the fancier standards, but signifi-
cantly faster than the typical SPI- or
UART-based make-do solution.
Pragmatic business factors also weigh
in U.K.-based Cyan’s favor. Cyan is a
spin-off from well-respected Cambridge
Consultants, spawning ground for other
credible players such as Bluetooth
powerhouse Cambridge Silicon Radio.
Thus, the eCOG1 isn’t some hand-
waving, back-of-the-napkin newbie
architecture. In fact, the core technol-
ogy of the eCOG1 has been in use for
USART/SPI/IR
/IrDA/I
2
C/SCI
Dual
UART
4-KB
iRAM
IntAct
EHI
PWM
12-bit
ADC
MUX
Power
on
reset
Switching multiplexer
V
DD
sensor
Temperature
sensor
Register
block
IRC
Interrupt
request
MMU
Code
cache
eCOG1
Low-power
CPU core
System
clock
64-KB
Flash
EPROM
EMI
PIF
GPIO
Timers
eICE
Data
Control
V
IN
4
Reset_In
Host computer
Clock inputs
External
triggers
29-bit I/O
or control
16/32-bit
Interface
24-bit
Addr/data
8-bit data
Channel A
Channel B
Stream
Up
Do
wn
Figure 3—An MMU, instruction cache, and the intriguing 180-Mbps IntAct interface are some of the unique fea-
tures that differentiate the eCOG1 from Cyan Technology.
Photo 2—The price of the eCOG1 eval hardware is
reasonable, especially considering that the device
includes a full-function (there are no time or code size
limits) C compiler.
www.circuitcellar.com
CIRCUIT CELLAR
®
Issue 144 July 2002
81
European operation) Adelante is also,
like Cyan, a startup that brings
impressive credentials to the table.
This time we’re looking at a 16-bit
foundry-independent core designed to
serve efficiency-minded DSP applica-
tions such as cell phones. Or is that a
96-bit core?
As you can see in Figure 5, the Saturn
core is indeed a VLIW under the hood.
It’s kind of a streamlined version of the
TI ’C6x I suppose. With two 16-bit mul-
tipliers, four 16-bit ALUs, two address
calculation units, a barrel shifter, loop
control, saturation, and bit manipula-
tion, there’s plenty of raw horsepower
on tap. Clock rates up to 210 MHz trans-
late to 420 million MACs per second.
Adelante’s chief claim to fame is
that the underlying VLIW is cleverly
fronted with a 16-bit ISA. Combining
the speed and circuit simplicity of a
VLIW with the code efficiency of a 16-
bit chip sounds great, but it sounded
to good to be true initially. However,
after talking to one of the designers, I
have a better understanding and appre-
ciation for the scheme. Conventional
16-bit instructions, typically used for
housekeeping, indeed use only one or
a few of the functional units at a time.
Yes, that seemingly goes against the
goal of fully utilizing every transistor
all the time, but who says you need
12-function units cranking away to
read a keypad or blink an LED?
AH
AL
UXH
UX
16 bits
16 bits
IXH
IX
UY
IY
PC
24 bits
AH/AL or A
Index x
Index y
Index x
Index y
Program
counter
User
mode
Interrupt
mode
Scratchpad
RAM
FFFF
FFE0
16 bits
64-K x 16
Data space
User mode:
Indexed
IY
Small address
range:
64K x 16
FFFFFF
16 bits
Large address
range:
16,320 x 16
0000
00FFFF: End of small
address range
000004: Interrupt routine
start address
000000: Reset address
Program space
T
Flags
8 bits
B
I
U
C
S
N
Z
Debug
flags
Interrupt
flags
Arithmetic/
logic flags
7
6
5
4
3
2
1
0
Figure 4—More bits doesn’t mean more complexity, as the 16-bit eCOG1 retro programmer model demonstrates.
Dual
Havard
VLIW
Program memory
16-bit instructions
Standard
instruction
ASI
table
Application-Specific
instructions
4(16-bit)/2(40-bit) ALUs
Application-Specific
Execution Units
PCU
LCU
MPY
0
MPY
1
ALU
0
ALU
1
ALU
2
ALU
3
SST
BRS
BMU
AXU
ACU
X
ACU
Y
Input registers
Product registers
Register files
Overflow registers
Address registers
DCU
16 bits
8 bits
96 bits
Figure 5—VLIW for the masses might be an apt description for Adelante’s Saturn DSP core.
82
Issue 144 July 2002
CIRCUIT CELLAR
®
www.circuitcellar.com
When it does come time to put the
pedal to the metal, as in DSP inner
loops, the eCOG1 uses Application-
Specific Instructions (ASIs) to shift
into full VLIW hyper-drive. One of the
16-bit opcodes is detected as invoking
an ASI, with the last eight bits index-
ing into a table of 256 96-bit VLIW
instructions.
As a core, the 256 × 96 table typi-
cally would be implemented in ROM
and filled with a predefined, fixed set
of VLIW instructions deemed most
useful in a particular design. However,
there is the possibility of implement-
ing some or all of the table as RAM.
This implies an intriguing ability sim-
ilar to reconfigurable computing to
dynamically redefine and modify the
ASI instruction set at run time.
Saturn offers three levels of upgrade
flexibility not found on a fixed function
chip. In addition to the aforementioned
ASIs, for even more performance
Application-Specific Execution Units
(AXU) can be added internally to the
core, piggybacking on the existing
data path and functional units. Beyond
AXUs, stand-alone Application-
Specific Coprocessors (ASCP) can
boost performance even further.
Adelante uses a Viterbi butterfly
inner-loop example to illustrate the
hierarchy of customization options.
The algorithm calls for two adds, two
subtracts, two compares, two status
updates, and four memory accesses
(i.e., 12 instructions on a conventional
chip). This can be swept into just two
ASIs at the cost of zero additional sili-
con. Adding an optimized AXU delivers
a further 4× boost over the ASI option.
That’s more than a 20× speed-up over
a non-accelerated design at the cost of
a mere 1000 or so additional gates.
Still not speedy enough? Drop in an
optimized ASCP and you can get up to
60 butterflies per clock cycle, if you’re
willing to throw 15K gates at the prob-
lem. That’s a whopping 600× speed-up
over the conventional baseline.
Customizing things is all well and
good, but getting an ASIC to work is
never easy to begin with. To simplify
matters, Adelante offers the Lunar
subsystem that combines the raw
Saturn core with the glue logic to
make integration easier.
Tom Cantrell has been working on
chip, board, and systems design and
marketing for several years. You may
reach him by e-mail at tom.cantrell@
circuitcellar.com.
REFERENCE
[1] T. Cantrell, “Sweet Sixteen,”
Circuit Cella
r 126, January 2001.
SOURCES
Saturn DSP Core
Adelante Technologies
32 16 391 411
www.adelantetech.com
IntAct
Amino Communications Ltd.
44 0 1954 784500
www.aminocom.com
eCOG1
Cyan Technology Ltd.
44 0 1954 207070
www.cyantechnology.com
MSP430x11x2, MSP430x12x2
Microcontrollers
Texas Instruments
(800) 336-5236
www.ti.com
So far, the Philips side of the
Adelante equation is plain to see. What
does Frontier Design bring to the
party? Perhaps a look at the Saturn C-
like assembly language is a clue (see
Listing 1). Note that Frontier’s prior
claim to fame was using C-like lan-
guages for hardware description.
Maybe we’re moving beyond the era
of mere programming and hardware
description languages toward some-
thing that might be described as a
“system definition language.”
The idea would be that an advanced
SDL tool would look at the big picture,
and then automatically (optimally)
partition the work between pure soft-
ware, pure hardware, and everything
in-between (including ASIs, AXUs,
and ASCPs). It seems like Adelante is
well equipped to lead the way in
breaking down some of the barriers
between hardware and software.
POWER OF TWO
There was a time when I might
have believed 16-bit chips were
doomed to be little more than a tran-
sition between their 8- and 32-bit
counterparts. But for now, considering
the Circuit Cellar survey numbers
and flurry of activity, I’d say it’s safe
to take 16-bit chips off the endan-
gered species list.
Indeed, if anything, the 8- to 32-bit
gap may be widening. Regarding vol-
ume, the center of gravity in the 8-bit
market is moving ever lower, thanks
to the less-than-$1 MCUs that are
sprinkled everywhere. Meanwhile,
32-bit chips can’t seem to escape the
tendency toward bloat that comes
with fancy OSs and performance-at-
any-price applications.
We’ve got 4- and 8-bit chips. We’ve
got 32- and 64-bit chips. The fact is,
the 16-bit gap between them is just
too big to ignore and it’s never going
away. Ultimately, nobody really cares
how many bits a chip has. What mat-
ters is whether or not the chip can do
the right job at the right price. Forget
the bits. Looking at the parts from TI,
Cyan, and Adelante, I see chips that
make sense, and that’s what counts.
I
Listing 1—Is it code or is it hardware? Adelante Technologies has its feet in both camps, so only the sili-
con knows for sure.
filter loop:
*px0 = ADCin;
x0 = *px0++, y0 = *py0++;
a0 = 0, p0 = x0 * y0, x0 = *px0++, y0 = *py0++;
repeat NTAPS-2
{ a0 += p0, p0 = x0 * y0, x0 = *px0++, y0 = *py0++;}
a0 += p0, p0 = x0 * y0, px0--;
a0 += p0;
r1 = round (a0);
ADCout = r1;
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CIRCUIT CELLAR
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Insert-ready sub-mini SBCs (small as 47x55 mm.) supporting the
Philips
achieved via GND circuitry, 6 to 8 layer PCB, by-
32 KB to 8 MB external SRAM & Flash (controller-dependent)
FlashTools enable on-board in-system (ISP) programming
C & CAN interfaces; ADC; Chip-Select signals
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www.circuitcellar.com to see who has what and how to get it!
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Interface Keypads, Switches, or RS-232 to your PC Keyboard Input
Up to 12 x 12 matrix Programmable RS-232 Port Macro Capability
The KE24 is the ultimate in flexibility. Inputs or serial data can
emulate any of the 101 keys from a standard keyboard.
Up to 9 x 9 matrix 2.5" x 3.0" Size PC Keyboard Port PCXT, AT Compatible
The KE18 combines a multitude of features with small size at an
economical price. Custom units available.
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1.9GHz Intel Pentium 4 Processor
60GB 7200RPM ATA 100 Hard Drive
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Prototyping Board with the CCS C compiler and libraries
Complete hardware kit with 56K modem and
examples using CCS C source code on a
PICmicro
embedded e-mail program and a web server.
A high order language with extraordinary optimization
specifically designed for the PICmicro
Internet Prototyping Board includes:
Our limited time offer also includes:
Debugger Unit (ICD)
CCS PCW Windows IDE Compiler
TCP/IP Lean book, by Jeremy Bentham
Access to all PICmicro hardware
features form C
Built-in libraries that work with all chips for RS232
C, discrete I/O and precision delays
90
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Solutions for all Your Video Needs
Hall Research Technologies, Inc.
Hall Research Technologies, Inc.
Hall Research Technologies, Inc.
Scan Converters & Video Scalers
Denver, Colorado, 720-940-5002
Embedded Networking Specialists
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Analog Techniques
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INDEX
85
Abacom Technologies
74
Accutech
85
ActiveWire, Inc.
22
All Electronics Corp.
88
Allied Components
85
Amazon Electronics
9
Amulet Technologies
92
AP Circuits
90
Appspec Computer Tech. Corp.
84
Atlantic Quality Design, Inc.
86
Avocet Systems, Inc.
85
Bagotronix, inc.
17,84
Basic Micro
55
CadSoft Computer, Inc.
89
CCS-Custom Computer Services
85
Cermetek Microelectronics Inc.
92
Conitec
37
Connecticut mircoComputer Inc.
91
Copeland Electronics Inc.
91
Cyberpak Co.
10
Cypress MicroSystems
C4
Dataman Programmers, Inc.
86
DataRescue
83
Decade Engineering
90
Delcom Engineering
87
DesignTech Engineering
90
Digital Products Co
88
Dreamtech Computers
The Advertiser’s Index with links to their web sites is located at www.circuitcellar.com under the current issue.
Page
1
Earth Computer Technologies
48
ECD (Electronic Controls Design)
86
EE Tools
(Electronic Engineering Tools)
75
EMAC, Inc.
48
ExpressPCB
84
FDI-Future Designs, Inc.
84
Hagstrom Electronics
90
Hall Research Technologies, Inc.
74
HI-TECH Software,LLC
91
HVW Technologies Inc.
90
IDSmicronet.com
87
IMAGEcraft
86,92
Intec Automation, Inc.
86
Intronics, Inc.
28
Intuitive Circuits, LLC
81
JED Microprocessors Pty Ltd.
64
JK microsystems
29
JR Kerr Automation & Engineering
28
LabJack Corp.
28
Lakeview Research
93
Lemos International
2
Link Instruments
93
Lynxmotion, Inc.
58
MaxStream
89
MCC (Micro Computer Control)
90
Microcross
89
Micro Digital Inc
92
microEngineering Labs, Inc.
23
Micromint Inc.
84
MicroSystems Development, Inc.
87
MJS Consulting
49
Mouser Electronics Inc.
26
MVS
86
Mylydia Inc.
65
NetBurner
95
Netmedia, Inc.
33
New Micros, Inc.
87
OKW Electronics Inc.
93
Ontrak Control Systems
C2
Parallax, Inc.
83
Phytec America LLC
83
Phyton, Inc.
91
Picofab Inc.
91
Pioneer Hill Software
85
Prairie Digital Inc.
89
Pulsar Inc.
91
R2 Controls
15
R4 Systems Inc.
7
Rabbit Semiconductor
90
Rad Proto
85
R.E. Smith
58
Remote Processing
89
RLC Enterprises, Inc.
88
RPA Electronics Design, LLC
86
Rutex
4
Saelig Company
Are You Grounded?
Driving the NKK Smartswitch—Part 2: Graphics and Text
Embedded Smarts Fix Analog Flaws
An Open-Source HCS Project
Digital Distributor-Less Ignition System
Robotics Corner: The CarolBot
RISCy Business: RISC Projects by Cornell Students
I Above The Ground Plane—PC Audio Bits
I From the Bench: SmartMedia—Part 3: Reading a File
I Silicon Update: FPGA News Flash
I Applied PCs: Building a Modular Programming Platform—Part 2: Building the PCB
Page
Page
Page
PREVIEW
145
ADVERTISER’S
Attention Advertisers:
September Issue Deadlines
Space Close: July 11
Material Due Date: July 18
Theme: Internet & Connectivity
3
Scott Edwards Electronics Inc.
88
Sealevel Systems Inc.
90
Senix Corp.
83
Sensory, Inc.
83
Signum Systems
87
SmartHome.com
91
Softools
39,57
Solutions Cubed
92
Spectrum Engineering
83
Square 1 Electronics
50
SUMBOX Pty Ltd.
16
Systronix
92
TAL Technologies
C3
Tech Tools
89
Techniprise Inc.
40,41
Technologic Systems
93
Technological Arts
88
Tern Inc.
90
Triangle Research Int’l Inc.
37
Trilogy Design
93
Weeder Technologies
91
Xilor Inc.
87
Z-World
29
Zagros Robotics
85
Zanthic Technologies Inc.
ver hear the one about the mid-level manager who arrives at the office every morning, flips on his com-
puter, and scans everything with anti-virus software? He scans the hard drive, system files, RAM, even the
CD-ROM. He runs three different anti-virus programs just to make sure. He does this every morning. He does
this
every day even though his computer has been turned off overnight. Who knows, perhaps something sneaked
in between the time he ran the anti-virus scans yesterday and turned on his computer again today. After all, you can’t be too careful
when it affects your job.
Besides, according to all of the daily news reports, it’s a cyber war out there. There are so many deadly computer viruses just
waiting for the opportunity to find an unprotected computer that your only defense is obsessive alertness. Constant media
reminders about the overwhelming cost and destruction from ILoveYou, Michelangelo, SirCam, and other Internet-born germs
make his palms sweat as he quickly yet conscientiously performs his daily search and destroy mission. Our mid-level manager is
determined that no two-bit cyber-thug or third-world terrorist is going to infiltrate his computer. After all, you can’t be too cautious
when it affects your job.
After the scanning is concluded, the leery manager downloads his e-mail from the company Intranet and proceeds to work. He
clicks on an e-mail that he sent to himself from his computer at home. Suddenly a strange and horrified look comes over his face.
He jumps up, rips the Ethernet connection out of the back of the computer and yanks the power cord out of the wall. Frantically, he
dials the network administrator and yells, “We’ve got a virus! My file is gone! It could only be a virus!”
Almost instantly, the network administrator appears at his desk, still panting from the long run down the hall. Viruses are no
minor event. Heading it off early might save hours of system rebuilds later. A quizzical look from the tech and our manager frantical-
ly exclaims, “It deleted my budget folder! I worked on it last night and I e-mailed it to myself this morning. I do this all the time. I work
on something at home and I e-mail it back to the office. This time, something ate it! It’s a deadly virus for sure!”
The network administrator reconnects the computer and sits down at the keyboard. After feverishly typing for 10 minutes, he
looks up and says, “You didn’t attach the file, sir. I looked at e-mail logs on the server. I can see your e-mail from home but there’s
no file. You forgot to attach it.” With that, he gathers up all the test disks he had expected to need, turns toward the office door, and
adds, “I’ll be down in the server room if you have any real problems.”
The manager frantically paces back and forth. “I never forget to send a file! It must be a virus. It must be a new one that’s really
insidious.” Quickly, he jumps in his chair and logs onto the Internet. “Now, if I can just find one of the anti-virus sites that details a
new one that deletes e-mail files. After all, you can’t be too careful when it affects your job,” he mutters.
As comical as this scenario sounds, I’m sure you’ve all met an individual like this or have heard of a similar situation. The con-
stant over-hyping about virus alerts and virus destruction in the media has created a paranoid culture within the ranks of some com-
puter users. Is it much ado about nothing? Certainly not.
Anti-virus software is an important application for all computer users. I’m not denying the gravity of the issue, but it shouldn’t
be cause for paranoia or fear at every newly announced bug in Outlook or Explorer. In the total population of computer users,
most have never seen or received a virus. In truth, the easiest virus path into a computer is a dumb user. Despite all of the warn-
ings about e-mail attachments as a source of viruses, a survey last year found that more than 40% of people would open an e-
mail appearing to be from someone they know if the following appeared in the subject line: “Great Joke,” “Look at this Message,”
or “Special Offer.”
Beware of the media propaganda and don’t suspect that every computer anomaly is generated by a virus. For intelligent users,
virus management is like avoiding being hit by a bus. Looking both ways before crossing the street is the same as deleting suspect
messages and filtering downloads. The best anti-virus technique is the expression of knowledge, not fortification.
Like Avoiding a Bus
INTERRUPT
e
steve.ciarcia@circuitcellar.com
96
Issue 144 July 2002
CIRCUIT CELLAR
®
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PRIORITY
STILL THE WORLD’S MOST
POWERFUL PORTABLE
PROGRAMMERS?
$795
inc 4mb ram
Orders received by 4pm will normally be despatched same day.
Surely not.
Surely someone somewhere
has developed a portable programmer that
has even more features, even greater
flexibility and is even better value for
money.
Actually, no. But don’t take our word for
it. Use the feature summary below to see
how other manufacturers’ products compare.
$1295
DATAMAN-48LV
• Plugs straight into parallel port of PC or
laptop
• Programs and verifies at 2, 2.7, 3.3 & 5V
• True no-adaptor programming up to 48
pin DIL devices
• Free universal 44 pin PLCC adaptor
• Built-in world standard PSU - for go-
anywhere programming
• Package adaptors available for TSOP,
PSOP, QFP, SOIC and PLCC
• Optional EPROM emulator
DATAMAN S4
• Programs 8 and 16 bit EPROMs,
EEPROMs, PEROMs, 5 and 12V FLASH,
Boot-Block FLASH, PICs, 8751
microcontrollers and more
• EPROM emulation as standard
• Rechargeable battery power for total
portability
• All-in-one price includes emulation
leads, AC charger, PC software, spare
library ROM, user-friendly manual
• Supplied fully charged and ready to use
S4 GAL MODULE
• Programs wide range of 20 and 24 pin
logic devices from the major GAL vendors
• Supports JEDEC files from all popular
compilers
SUPPORT
• 3 year parts and labor warranty
• Windows/DOS software included
• Free technical support for life
• Next day delivery - always in stock
Still as unbeatable as ever. Beware of
cheap imitations. Beware of false
promises. Beware of hidden extras.
If you want the best, there’s still only one
choice - Dataman.
Order via credit card hotline - phone
today, use tomorrow.
Alternatively, request more detailed
information on these and other market-
leading programming solutions.
NEW MODEL
MONEY-BACK
30 DAY TRIAL
If you do not agree that these truly are the
most powerful portable programmers you can
buy, simply return your Dataman product
within 30 days for a full refund
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