5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
PINS FOR MAC MODULES
B
C
E
BC847
Transistor Footprint
99.07.02 First release of partlist
Revision list:
99.07.05 Complex 27Mhz circuit replaced by oscillator
Mechanical
Thursday, January 20, 2000
A3
1030-00003-4
1.0
1030 Mechanical Parts
9
1
Date:
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing
is copyright of
FORCE Electronics A/S Denmar
k.
Legal actions will be taken against any company u
sing or
copying the design/ideas or information contai
ned on this
drawing without prior written permiss
ion.
MT4
HFC2580-Hole
1
1
MT5
HFC2580-Hole
1
1
MT6
HFC2580-Hole
1
1
MT7
HFC2580-Hole
1
1
TH3
Toolinghole
1
1
TH2
Toolinghole
1
1
TH1
Toolinghole
1
1
FM1
Fiducial
1
1
FM2
Fiducial
1
1
MT1
MountingHole
1
1
MT3
MountingHole
1
1
PCB1
#1030-19003
GND1
gnholed
1
1
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
0$,1
Thursday, January 20, 2000
A3
1030-00003-4
1.0
DVB Receiver
9
2
Date:
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing
is copyright of
FORCE Electronics A/S Denmar
k.
Legal actions will be taken against any company u
sing or
copying the design/ideas or information contai
ned on this
drawing without prior written permiss
ion.
Power
50HZ
SmartCardIf
Vpp low
-Power A
-Power B
Vpp A
Vpp B
Card I/O A
Card I/O B
Card Clock A
Card Reset A
Card det A
Card det B
Card Reset B
Card Clock B
Micro&Mac
BBVIDEO
MACPAL
ROUT
GOUT
BOUT
RDIG
GDIG
BDIG
FBL
Vpp low
-Power A
-Power B
Vpp A
Vpp B
Card I/O A
Card I/O B
Card Clock A
Card Reset A
Card Reset B
Card Clock B
Card det B
Card det A
MACYOUT
MACCOUT
CVBSDIG
CDIG
YDIG
DIG-AUD-L
DIG-AUD-R
/D_WAIT
D_RD/WR
/D_CS2
IR RX SCART
I2CSCL
I2CSDA
-RESET3.3V
CLK 27MHZ
TSCA_CLK
TSCA_START
TSCA_VALID
TSCA_D[0..7]
DA[2..23]
/INT0
DD[0..7]
/D_BE2
/D_BE3
MacLeftAudio
MacRightAudio
SCTX
SCRX
/RESET5V
50HZ
50HZ
50HZ
50HZ
50HZ
50HZ
FRONTEND-CA
I2CSDA
I2CSCL
BBVIDEO
/D_CS2
D_RD/WR
/D_WAIT
-RESET3.3V
CLK 27MHZ
TSCA_CLK
TSCA_START
TSCA_VALID
TSCA_D[0..7]
DA[2..23]
/INT0
DD[0..7]
/D_BE2
/D_BE3
/RESET5V
Scart
MACPAL
ROUT
GOUT
BOUT
RDIG
GDIG
BDIG
I2CSCL
I2CSDA
IR RX SCART
FBL
MACCOUT
MACYOUT
YDIG
CDIG
CVBSDIG
DIG-AUD-R
DIG-AUD-L
MacLeftAudio
MacRightAudio
SCRX
SCTX
TSCA_D[0..7]
DA[2..23]
DD[0..7]
MACPAL
ROUT
GOUT
BOUT
RDIG
GDIG
BDIG
BBVIDEO
IR RX SCART
FBL
I2CSDA
I2CSCL
Card Clock A
Card I/O B
Card Reset B
Card det A
Vpp B
Vpp A
Card det B
Vpp low
Card I/O A
-Power A
-Power B
Card Reset A
Card Clock B
MACYOUT
MACCOUT
YDIG
CDIG
CVBSDIG
DIG-AUD-R
DIG-AUD-L
/D_WAIT
D_RD/WR
/D_CS2
-RESET3.3V
CLK 27MHZ
TSCA_CLK
TSCA_START
TSCA_VALID
/INT0
/D_BE2
/D_BE3
MacLeftAudio
MacRightAudio
SCTX
SCRX
/RESET5V
50HZ
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
&$
Thursday, Ja nuary 20, 2000
A2
1030-00003-4
1.0
LNB inte rface
9
3
Date :
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing is copyr
ight of
FORCE Electronics A/S Denmar k.
Legal actions will be taken against any company using
or
copying the design/ideas or information contained on
this
drawing without prior written permission
.
DA[2.. 14]
TSCA_D[0..7]
M
AB[
0
..
1
4
]
DA[2.. 14]
M
AA[
0
..
1
4
]
PCMDA[0..7]
PCMDA[0..7]
MDIAD[0..7]
MDIBD[0..7]
MDOBD[0..7]
MDIAD[0..7]
MIBPB[0..7]
MDOAD[0..7]
MDOAD[0..7]
TS299[ 0..7]
MDIBD[0..7]
/D_BE2
MDOBD5
MAB2
/CE1B
/REGA
MDOAD1
MAB9
MDIAD4
MAB4
MDOBD7
MDOBD0
MOCLKA
MOSTRTA
MDIAD0
/IRQB
/IOWR A
DA9
/CE1A
MAB13
/IOWRB
MDIAD2
MDOAD3
MOVALB
MDIAD6
/REGB
TSCA_D4
TSCA_D1
MDOAD1
MIVALB
MAB1
/IORD A
MDIAD7
MDOBD6
MAB4
MAB14
MDOAD7
MDOBD4
MDOBD3
MAB5
MAB11
MDOBD2
MDOBD1
MAB3
MDOBD1
/WEB
TSCA_D5
DA10
MDOAD3
MICLKB
MDOBD7
/RESETPCCB
TSCA_D0
DA2
DA13
MAB12
MAB5
MDOBD2
/REGA
MAB8
MDIAD5
MISTRTB
MDOBD6
DA6
/WEA
MDOAD6
MAB6
MAB7
MDIAD6
MDOAD5
MDIAD3
/WEA
MDOAD4
MDIAD1
MAB3
MDOBD5
MAB7
MDIAD7
MAB10
MDIAD2
TSCA_D7
/IORD A
DA3
MDOBD4
MDIAD5
MDIAD3
MDOAD2
MDOAD0
MOSTRTB
/OEA
MAB2
MAB0
TSCA_D2
/CE1B
/D_BE3
DA7
MIVALA
MDOAD2
MDIAD4
MAB14
/RESETPCCA
/OEB
MDIAD0
MAB13
MAB10
/CE1A
DA5
/IORD B
MICLKA
MDOAD6
/OEA
DA11
MAB1
MAB12
MDOAD0
MDOAD7
TSCA_D3
DA4
DA14
MOCLKB
MAB8
MAB0
MDOAD4
MDOAD5
MDOBD3
MAB11
TSCA_D6
DA8
DA12
MISTRTA
/IOWR A
MDOBD0
MAB6
MDIAD1
MAB9
DD0
DD1
DD2
DD3
DD6
DD4
DD5
DD7
DA2
DA16
DA17
/WAITB
/WAITA
/WAITB
/REGB
/IOWRB
/WEB
/IORD B
/OEB
/D_BE2
MAA9
DA9
MAA13
MAA1
MAA4
MAA5
DA10
DA2
DA13
MAA12
DA6
MAA3
MAA7
MAA10
DA3
MAA2
/D_BE3
DA7
MAA14
DA5
DA11
DA4
DA14
MAA8
MAA0
MAA11
DA8
DA12
MAA6
/WAITA
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
PCMDA0
PCMDA1
PCMDA2
PCMDA3
PCMDA4
PCMDA5
PCMDA6
PCMDA7
PCMDA2
PCMDA3
PCMDA5
PCMDA7
/IRQA
MDIBD6
MDIBD0
MDIBD5
MDIBD2
MDIBD1
MDIBD3
MDIBD7
MDIBD4
MOVALA
TSCA_D7
TSCA_D6
TSCA_D5
TSCA_D4
TSCA_D3
TSCA_D2
TSCA_D1
TSCA_D0
MOCLKA
MOSTRTA
MOVALA
MDIBD6
MDIBD0
MDIBD4
MDIBD7
MDIBD2
MDIBD3
MDIBD5
MDIBD1
TS2997
TS2996
TS2995
TS2994
TS2993
TS2992
TS2991
MIBPB7
MIBPB6
MIBPB5
MIBPB4
MIBPB3
MIBPB2
MIBPB1
MIBPB0
MIBPB7
MIBPB6
MIBPB5
MIBPB4
MIBPB3
MIBPB2
MIBPB1
MIBPB0
MOCLKB
MOSTRTB
MOVALB
MICLKA
MIVALA
MISTRTA
MIBPB7
MIBPB6
MIBPB5
MIBPB4
MIBPB3
MIBPB2
MIBPB1
MIBPB0
MIBPB7
MIBPB6
MIBPB5
MIBPB4
MIBPB3
MIBPB2
MIBPB1
MIBPB0
TS2993
TS2995
TS2997
TS2996
TS2992
TS2991
TS2990
TS2994
TS2990
PCCARDON
/AOE_A
/AOE_B
/BYPSSB
/INPUTA
/BYPSSA
/INPUTB
/INPUTA
/INPUTA
/INPUTA
/BYPSSA
/BYPSSA
/INPUTB
/CDA
/CDB
/CDB
/CDA
/IRQB
/IRQA
/INPUTA
M
IBPC
L
K
/INPUTB
M
IBPVAL
/INPUTB
MISTRTB
MICLKB
/BYPSSB
/INPUTB
M
IBPST
R
T
/BYPSSB
MIVALB
/RESETPCCB
MISTR
MISTR
/RESETPCCA
PCMDB2
PCMDB7
PCMDB4
PCMDB1
PCMDB3
PCMDB3
PCMDB0
PCMDB0
PCMDB6
PCMDB5
PCMDB[0..7]
PCMDB[0..7]
PCMDB7
/AOE_A
/AOE_B
/CS_PCCA
/CS_PCCB
/CS_PCCA
/CS_PCCB
/CS_PCCB
/CS_PCCA
/CS_PCCA
/CS_PCCB
PCMDA0
PCMDA1
PCMDA4
PCMDA6
PCMDB1
PCMDB2
PCMDB4
PCMDB5
PCMDB6
TS299CLK
4
TS299[ 0..7]
4
TS299START
4
TS299VALID
4
-RESET3.3V
4,6
I2CSDA
4,5,6 ,8
I2CSCL
4,5,6 ,8
5VPCCARDB
5V
3.3 V
3.3 V
3.3 V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3 V
3.3 V
3.3 V
3.3 V
5V
5VPCCARDB
5VPCCARDB
5V
5V
5V
5V
3.3 V
3.3 V
3.3 V
C9
100nF
C11
100nF
R126
0
U15
CXD1957Q
18
17
47
46
19
20
21
44
43
38
36
37
45
64
40
62
41
60
61
56
55
54
53
51
50
49
48
10
35
7
3
6
5
4
25
26
27
28
29
30
31
34
24
39
9
8
57
59
58
67
66
65
13
11
14
16
22
77
76
75
74
71
70
69
68
15
1
78
79
80
33
73
2
12
23
32
42
52
63
72
SI1
SI0
SI2
SI3
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
WAIT_A
CE1_A
REG_A
OE_A
WE_A
IORD_A
IOWR_A
D0_A
D1_A
D2_A
D3_A
D4_A
D5_A
D6_A
D7_A
WAIT_B
CE1_B
REG_B
OE_B
WE_B
IORD_B
IOWR_B
D0_B
D1_B
D2_B
D3_B
D4_B
D5_B
D6_B
D7_B
AOE_A
DOE_A
AOE_B
DOE_B
MISTR
TSSTR
TSCK
TEST
MODE
CPU
IRQ
ACK
CS
RW
CK
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
SEL0
SEL1
HA0
HA1
HA2
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C7
100nF
C3
100nF
C10
100nF
R142
39
C13
100nF
R143
39
U13
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
R2
10K
C2
100nF
PCMCIA_A
PCMCIA_B
U4
DBLPCMCIA
20
19
46
47
48
49
50
53
54
55
56
57
62
63
64
65
66
37
38
39
40
41
61
7
42
9
15
44
45
60
16
68
35
34
1
30
31
32
2
3
4
5
6
29
28
27
26
25
24
23
22
12
11
8
10
21
13
14
36
67
43
59
18
52
58
33
51
17
88
114
87
115
116
117
118
121
122
123
124
98
99
100
70
71
72
73
74
97
96
95
94
93
92
91
90
80
79
76
78
89
81
82
104
135
111
127
86
120
126
101
119
85
125
131
130
132
133
134
105
106
107
108
109
129
75
110
77
83
112
113
128
84
136
103
102
69
MICLK
MIVAL
MISTRT
MDI0
MDI1
MDI2
MDI3
MDI4
MDI5
MDI6
MDI7
MOCLK
MOVAL
MOSTRT
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
REG
CE1
CE2
OE
WE/PGM
IORD
IOWR
INP_ACK
IREQ
GND
GND
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
CD1
CD2
VTG_SENSE
WAIT
VPP1
VPP2
RESET
IOCS16
VCC
VCC
MICLK
MISTRT
MIVAL
MDI0
MDI1
MDI2
MDI3
MDI4
MDI5
MDI6
MDI7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
CD1
CD2
VTG_SENSE
WAIT
VPP1
VPP2
RESET
IOCS16
VCC
VCC
MOCLK
MOSTRT
MOVAL
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
REG
CE1
CE2
OE
WE/PGM
IORD
IOWR
INP_ACK
IREQ
GND
GND
GND
GND
R144
39
R127
10K
C4
100nF
R157
DUMMY
U7
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
U6
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
U5
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
R4
4.7 K
U9
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
U8
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
U3
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
C5
100nF
U2
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
U10
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
C12
100nF
R1
10K
C6
100nF
U1
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
C15
100nF
U11
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
R145
39
R7
47K
R146
39
R141
39
Q1
SI443 1DY
1
2
3
4
5
6
7
8
S1
S2
S3
G
D1
D2
D3
D4
U12
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
C8
100nF
U14
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
C112
100nF
C16
100nF
U32
74LVX244
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
R3
10K
C18
100nF
C17
100nF
C1
100nF
R6
10K
TSCA_START
6
CLK 27MHZ
6
TSCA_CLK
6
/INT0
6
TSCA_VALID
6
/D_CS2
6
TSCA_D[0..7]
6
D_RD/ WR
6
I2CSDA
4,5,6 ,8
-RESET3.3V
4,6
I2CSCL
4,5,6 ,8
/D_WAIT
6
DD[0..7 ]
6
/D_BE2
6
/D_BE3
6
DA[2.. 23]
6
/RESET5V
6
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Frontend Interface
Thursday, January 20, 2000
A3
1030-00003-4
1.0
Frontend Interface
9
4
Date:
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing
is copyright of
FORCE Electronics A/S Denmar
k.
Legal actions will be taken against any company u
sing or
copying the design/ideas or information contai
ned on this
drawing without prior written permiss
ion.
TS299[0..7]
TS2990
TS2991
TS2992
TS2993
TS2994
TS2995
TS2996
TS2997
TS299CLK
3
TS299VALID
3
TS299[0..7]
3
TS299START
3
I2CSCL
5,6,8
I2CSDA
5,6,8
-RESET3.3V
6
3.3V
12V
22V
30V
5V
3.3V
12V
22V
30V
5V
JP5
POWER PINHEADER
1
2
3
4
5
6
1
2
3
4
5
6
J1
IDCBOXHEADER40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BBVIDEO
5
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
0$&
Thursday, January 20, 2000
A3
1030-00003-4
1.0
Mac section
9
5
Date:
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing
is copyright of
FORCE Electronics A/S Denmar
k.
Legal actions will be taken against any company u
sing or
copying the design/ideas or information contai
ned on this
drawing without prior written permiss
ion.
I2CSDA
4,6,8
I2CSCL
4,6,8
IMCLK
6
IMIO
6
IMDAT
6
-EXTRESET
6
BDAT
6
BCLK
6
TSYNC
6
MAC5VOFF
6
5V
12V
J6
IDCBOXHEADER40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
JP6
POWER PLUG 4_S
1
2
3
4
1
2
3
4
MACPAL
8
ROUT
8
GOUT
8
BOUT
8
MACYOUT 8
MACCOUT 8
MacLeftAudio 8
MacRightAudio 8
BBVIDEO 4
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
CD
DTR
D
O
N
O
T
MOUNT
Supported Flash
Fujitsu 8Mbit: MBM29LV800TA
Fujitsu 16Mbit: MBM29LV160T
AMD 8Mbit: AM29LV800B_T
AMD 16Mbit: AM29LV160B_T
ST: ?
Leaded and
SMD type
Mount only
ONE
Micro
Thur sday, January 20, 2000
Custom
1030-00003-4
1.0
Micro section
9
6
Date:
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing is copy
right of
FORCE Electronics A/S Den
mark.
Legal actions will be taken against any company
using or
copying the design/ideas or information contained
on this
drawing without prior written permi
ssion.
PDO[0..7]
INTRTS
INTTXD
INTCTS
INTRXD
PBIT2
PE
-TACK
TBUSY
SLCT
PDO0
PDO3
PDO6
PDO4
PDO2
PDO1
PDO5
PDO7
-EXTRESET
PD
O
6
PD
O2
PD
O
3
PD
O
4
PD
O
7
PD
O
0
PD
O5
PD
O1
TSCA_D[0..7]
TS
CA
_
D
7
TS
CA
_
D
5
TS
CA
_
D
3
TS
CA
_
D
4
TS
CA
_
D
6
TS
CA
_
D
2
TS
CA
_
D
0
TS
CA
_
D
1
TBUSY
SLCT
27MHZ PWM
PE
-INIT
-ERR
-TSTB
-TACK
-TAFD
-SLIN
BCLK
IR RX IN
INTRTS
INTTXD
BSE1
INTCTS
BDAT
BSE2
TSYNC
INTRXD
PANEL IR TX
TMS
TDI
TDO
TRIGIN
TCK
TRIGOUT
-TRST
I2CSCL
I2CSDA
SPEE
D
0
CLK 27MHZ
SPEE
D
1
TRIG
IN
TRIG
O
U
T
PANEL IR RX
SDD[0..15]
SDA[0..11]
SDDQML
SDD13
SDD0
SDD1
SDA10
SDD14
SDA0
SDA0
SDA1
SDD5
SDA9
SDA4
SDA5
SDA9
SDD13
SDA0
SDA7
SDA11
SDD6
SDA2
SDD8
SDA1
SDD15
SDD10
SDD7
SDA4
/SDRAS
SDD6
SDD14
SDA11
SDA10
SDA5
SDD9
SDA3
SDD15
/SDCS1
SDA8
SDA2
SDA5
SDD0
SDD12
SDD3
SDA4
SDD7
SDD3
SDD9
SDD4
SDD8
SDD0
SDA7
SDD8
SDD4
SDD10
SDD2
/SDWE
SDD15
SDD10
SDD2
SDCLK
SDD12
SDD13
SDD1
SDA7
SDA9
SDA8
SDA6
SDD1
SDD7
SDA3
SDD4
SDA8
SDD11
SDD2
SDD14
SDD6
SDA6
SDA2
SDD9
SDD11
SDA3
SDD5
SDA6
SDD12
SDD11
SDD5
SDD3
SDA11
SDA1
SDA10
/SDCAS
/SDCS0
PANEL IR RX
I2CSCL
I2CSDA
DA[2..23]
DD[0..31]
/D_OE
/D_CAS2
DD2
1
DA
9
DA
2
0
DD28
DD10
DD6
DD1
DA9
DD5
DD24
DA5
DA14
DD22
/D_RAS0
DD1
DD1
5
DD2
4
DA
1
0
DA8
DA6
DD11
DA2
DA11
DD3
DA10
DD5
DD1
0
DA2
DA8
DA20
DA13
DD26
DA6
DD23
DD19
DD6
DD1
2
DD2
3
DA
1
2
DA
1
4
DD14
DA8
DD7
DD30
/D_WAIT
DD3
1
DA
3
DA
2
2
DD30
DD29
DD27
DA7
DA5
DD13
DD12
DA10
DA17
DA18
DA9
/D_CAS3
DD1
8
DA
7
DD16
DD15
DD5
DA3
DA13
DD21
DD8
DD12
DD27
DD18
DD2
DA
1
5
DD25
DD18
DD9
DA3
DA14
DD0
DD25
/D_BE2
DD2
9
DA
2
1
DA
2
3
DA3
DD2
DD2
DD31
DA2
DA3
DA4
DA7
DA15
DD17
/D_CS2
DD3
DD2
5
DD2
6
DD2
8
DA
1
8
DD20
DA7
DD0
DD8
DA4
DA6
DA7
DA12
DA15
DA17
DD1
3
DD2
2
DA
4
DD17
DA21
DD7
DD1
1
DD3
0
DA
5
DA
6
DA
1
3
DD13
DD7
DD3
DA11
DA9
DA4
DA2
DA19
DD16
/D_BE3
DD9
DD1
4
DD1
7
DD1
9
DA
1
7
DD31
DD24
DD22
DD19
DD4
DA10
DD10
DA21
DA16
DD4
DA11
DA12
DD0
DD2
0
DD2
7
DA
1
9
DD21
DA10
DD14
DD9
DA19
DD6
DA20
DA16
DD20
/D_CAS1
DA
1
1
DA6
-RESET3.3V
DD29
-RESET3.3V
DA18
DA
8
DA
1
6
DA9
DA5
DA4
DA8
/D_CAS0
DD4
DD1
6
DA
2
DD26
DD23
DA11
DD11
DD8
DD15
DA5
DD1
DD28
PANEL IR TX
D_RD/WR
/D_CS_ROM
/D_BE1
/RI
/RI
-JTAGRST
BSE1
BSE2
27MHZ PWM
-JTAGRST
SCRX
SCTX
SC
T
X
SC
R
X
/RESET5V
SDDQMU
-RESET3.3V
PBIT1
-INIT
-TSTB
-TAFD
PBIT0
-ERR
-SLIN
PBIT3
PBIT4
PBIT7
PBIT6
PBIT5
50HZINT
50HZINT
IMDAT
5
-EXTRESET
5
BDAT
5
BCLK
5
TSYNC
5
IMCLK
5
IMIO
5
I2CSCL
4,5,8
I2CSDA
4,5,8
/D_BE2
3
/D_BE3
3
MAC5VOFF
5
5V
5V
5V
5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
VCC
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
3.3V
3.3V
3.3V
R149
DUMMY
BS2
DUMMY
U27
MB81F161622B
21
22
23
24
27
28
29
30
31
32
20
19
2
3
5
6
8
9
11
12
39
40
42
43
45
46
48
49
15
16
17
18
34
35
14
36
37
33
1
4
7
10
13
25
50
26
38
41
47
44
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WE
CAS
RAS
CS
CKE
CLK
DQML
DQMU
NC.
NC.
VCC
VSSQ
VCCQ
VSSQ
VCCQ
VCC
VSS
VSS
VCCQ
VSSQ
VSSQ
VCCQ
R116
39
R104
390
R3A
0
U16C
74LVX02
8
9
10
R117
39
U16A
74LVX02
3
2
1
L7
4.7uH
C113
68pF
C89
82pF
C114
68pF
C53
100nF
R82
390
U21
TC54-4.6V
1
2
3
Vout
Vin
Vs
s
C84
82pF
R56
10K
C115
68pF
C54
100nF
U26
MB81F161622B
21
22
23
24
27
28
29
30
31
32
20
19
2
3
5
6
8
9
11
12
39
40
42
43
45
46
48
49
15
16
17
18
34
35
14
36
37
33
1
4
7
10
13
25
50
26
38
41
47
44
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WE
CAS
RAS
CS
CKE
CLK
DQML
DQMU
NC.
NC.
VCC
VSSQ
VCCQ
VSSQ
VCCQ
VCC
VSS
VSS
VCCQ
VSSQ
VSSQ
VCCQ
C104
100nF
C55
100nF
R83
390
C105
100nF
C82
DUMMY
C56
100nF
R74
0
C102
100nF
X2
32.
768
k
H
z
C57
100nF
C80
82pF
C103
100nF
C49
27pF
L8
4.7uH
C58
100nF
C101
100nF
U16B
74LVX02
5
6
4
C50
27pF
C59
100nF
J7
IDCBOXHEADER26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C96
100nF
R88
390
C60
100nF
AGC
Dem.
H3
DUMMY
3
2
1
Vs
GN
D
Out
C63
100nF
C98
100nF
C45
100nF
R86
10K
R89
390
C64
100nF
L2
22uH
C65
100nF
C71
100nF
R85
2.7K
C83
82pF
R139
DUMMY
C66
100nF
R84
2.7K
R
131
10K
C67
100nF
C68
100nF
C69
100nF
+
C44
10uF
R136
10K
5%
C70
100nF
R59
10K
JP3
HEADER10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
R80
390
+
C51
10uF
R118
47K
R79
390
X3
DUMMY
1
4
3
2
V CONT
VCC
OUT
GND
R119
47K
D7
DALC112S1
6
8
1
2
3
4
5
7
H
L
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
U16D
74LVX02
11
12
13
C93
82pF
TP2
Testpoint
1
TP
R147
68
C91
DUMMY
U24
STI5512
U1
2
K17
L20
L1
Y10
V11
W1
0
K2
K1
K3
A3
B3
Y11
W11
C1
4
A15
B15
C1
5
D1
5
A16
B16
C1
6
A17
B17
C1
7
D1
7
A18
B18
B19
A19
A20
B20
C2
0
C1
9
C1
8
D2
0
A5
B5
C5
A6
B6
C6
A7
B7
C7
D7
B8
C8
A9
B9
C9
D9
A10
B10
C1
0
A11
B11
C1
1
D1
1
A12
B12
C1
2
A13
B13
C1
3
D1
3
A14
B14
G20
K19
K18
J18
D19
D18
E20
E19
E18
F17
F20
F19
F18
K20
G19
G18
H20
H19
J20
J19
H1
7
W15
V15
Y14
W14
V14
U14
Y13
W13
V13
Y12
W12
V12
R18
T20
T19
T18
T17
U20
U19
U18
V20
V19
W20
Y20
W19
Y19
W18
V18
Y15
U16
V16
W16
Y16
W17
V17
Y17
Y18
L19
M2
0
M1
9
L18
M1
8
M1
7
N2
0
N1
9
N1
8
P20
P19
P18
H1
G4
G3
G2
F3
F2
F1
E1
C2
C1
D3
D2
D1
E4
E3
E2
H2
J4
J3
J2
H3
J1
W5
W4
V6
V5
V4
Y4
U6
Y5
Y6
V7
W7
W8
Y8
D5
C4
V9
V2
W1
V3
W2
Y1
W3
Y2
Y3
C3
V10
U10
Y9
W9
V8
U8
Y7
L3
A2
B2
B1
A1
L2
A4
B4
D4
H4
M4
T4
D8
U7
D1
2
U1
1
D1
6
U15
G17
L17
R1
7
F4
K4
P4
U5
D6
U9
D1
0
D1
4
U1
3
E17
J1
7
N1
7
U1
7
J9
J10
J11
J12
K9
K10
K11
K12
L9
L10
L11
L12
M9
M10
M11
M12
R1
9
R2
0
P17
H18
M1
N1
P3
N3
N2
N4
M2
M3
R2
R4
R3
P1
P2
R1
T3
U3
U4
U2
T1
T2
U1
V1
L4
G1
W6
A8
CL
O
C
K
IN
SPEED
SEL1
SPEED
SEL0
/R
ESET
CP
UA
S
/TRIG
IN
C
P
U
R
ESET
E
RRO
UT/TRIG
O
U
T
L
P
CL
O
C
K
IN
LP C
L
OC
K OSC
RTC V
D
D
INT1
INT0
OS_LINK_IN
OS_LINK_OUT
ME
M_
A
DDR_
2
3
ME
M_
A
DDR_
2
2
ME
M_
A
DDR_
2
1
ME
M_
A
DDR_
2
0
ME
M_
A
DDR_
1
9
ME
M_
A
DDR_
1
8
ME
M_
A
DDR_
1
7
ME
M_
A
DDR_
1
6
ME
M_
A
DDR_
1
5
ME
M_
A
DDR_
1
4
ME
M_
A
DDR_
1
3
ME
M_
A
DDR_
1
2
ME
M_
A
DDR_
1
1
ME
M_
A
DDR_
1
0
ME
M_
A
DDR_
9
ME
M_
A
DDR_
8
ME
M_
A
DDR_
7
ME
M_
A
DDR_
6
ME
M_
A
DDR_
5
ME
M_
A
DDR_
4
ME
M_
A
DDR_
3
ME
M_
A
DDR_
2
ME
M_
DA
TA
_
3
1
ME
M_
DA
TA
_
3
0
ME
M_
DA
TA
_
2
9
ME
M_
DA
TA
_
2
8
ME
M_
DA
TA
_
2
7
ME
M_
DA
TA
_
2
6
ME
M_
DA
TA
_
2
5
ME
M_
DA
TA
_
2
4
ME
M_
DA
TA
_
2
3
ME
M_
DA
TA
_
2
2
ME
M_
DA
TA
_
2
1
ME
M_
DA
TA
_
2
0
ME
M_
DA
TA
_
1
9
ME
M_
DA
TA
_
1
8
ME
M_
DA
TA
_
1
7
ME
M_
DA
TA
_
1
6
ME
M_
DA
TA
_
1
5
ME
M_
DA
TA
_
1
4
ME
M_
DA
TA
_
1
3
ME
M_
DA
TA
_
1
2
ME
M_
DA
TA
_
1
1
ME
M_
DA
TA
_
1
0
ME
M_
DA
TA
_
9
ME
M_
DA
TA
_
8
ME
M_
DA
TA
_
7
ME
M_
DA
TA
_
6
ME
M_
DA
TA
_
5
ME
M_
DA
TA
_
4
ME
M_
DA
TA
_
3
ME
M_
DA
TA
_
2
ME
M_
DA
TA
_
1
ME
M_
DA
TA
_
0
MEM_RDNOTWR
MEM_REQ
MEM_GRANT
MEM_WAIT
/MEM_CAS_3
/MEM_CAS_2
/MEM_CAS_1
/MEM_CAS_0
/MEM_RAS_3
/MEM_RAS_2
/MEM_RAS_1
/MEM_RAS_0
/MEM_CS_ROM
/MEM_OE
/MEM_BE_3
/MEM_BE_2
/MEM_BE_1
/MEM_BE_0
BOOT_SRC_1
BOOT_SRC_0
PR
OC
_C
LOC
K
_OU
T
SD_AD_11
SD_AD_10
SD_AD_9
SD_AD_8
SD_AD_7
SD_AD_6
SD_AD_5
SD_AD_4
SD_AD_3
SD_AD_2
SD_AD_1
SD_AD_0
SD_DQ_15
SD_DQ_14
SD_DQ_13
SD_DQ_12
SD_DQ_11
SD_DQ_10
SD_DQ_9
SD_DQ_8
SD_DQ_7
SD_DQ_6
SD_DQ_5
SD_DQ_4
SD_DQ_3
SD_DQ_2
SD_DQ_1
SD_DQ_0
SD_CLOCK_IN
SD_CLOCK_OUT
/SD_WE
/SD_CAS
/SD_RAS
/SD_CS_1
/SD_CS_0
SD_DQ_MU
SD_DQ_ML
T
S
I BYT
E C
L
K
T
S
I BC
LK VALI
D
T
S
I PKT
C
L
K
TS
I E
RRO
R
TS
I DA
TA
7
TS
I DA
TA
6
TS
I DA
TA
5
TS
I DA
TA
4
TS
I DA
TA
3
TS
I DA
TA
2
TS
I DA
TA
1
TS
I DA
TA
0
1284_D
AT
A_7
1284_D
AT
A_6
1284_D
AT
A_5
1284_D
AT
A_4
1284_D
AT
A_3
1284_D
AT
A_2
1284_D
AT
A_1
1284_D
AT
A_0
1284_/SELECT_IN
1284_/INIT
1284_/FAULT
1284_/AUTOFD
1284_SELECT
1284_P_ERROR
1284_BUSY
1284_/ACK
1284_/STROBE
TDI
TDO
TMS
TCK
/T_RST
PIO_04_SC1RST
PIO_01_ASC0RXD
PIO_07_SC1DETEC
PIO_03_SC1CLK
PIO_00_ASC0TXD
PIO_02_SC1CLKGE
PIO_06_SC1DIR
PIO_05_SC1CMD
PIO_10_SSC0_MTS
PIO_11_SSC0_MRS
PIO_12_SSC0SCLK
PIO_13_PWM_OUT0
PIO_14_PWM_OUT1
PIO_15_ASC1TXD
PIO_16_ASC1RXD
PIO_17_PWM_OUT2
PIO_20_ASC2TXD
PIO_21_ASC2RXD
PIO_22_SC0CLKGE
PIO_23_SC0CLK
PIO_24_SC0RST
PIO_25_SC0CMD
PIO_26_SC0DIR
PIO_27_SC0DETEC
PIO_37_1284_OUT
PIO_36_COMP_OUT
PIO_35_CAPT_IN2
PIO_34_CAPT_IN1
PIO_33_CAPT_IN0
PIO_32_SSC1SCLK
PIO_31_SSC1MRST
PIO_30_SSC1MTSR
PIO_47_TTEXTDAT
PIO_46_INT3
PIO_45_INT2
PIO_44_1284HOST
PIO_43_1284PERI
PIO_42_TTEXTCLK
PIO_41_ASC3RXD
PIO_40_ASC3TXD
YC
7
TTXT_EVEN/ODD
TTXT_HSYNC
CFC
YC
0
YC
6
YC
1
YC
5
YC
2
SD_AD_12
/SDRAMCS0
YC
3
YC
4
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AU
X_C
L
K_OU
T
VC
C
_
VPLL
GND_VPLL
/MEM_CS2
PCM_LR_CLK
PCM_DATA
PCM_CLK_OUT
PCM_CLK_IN
AC3_REQ
AC3_PTS_STB
/HSYNC
ODD_EVEN
CV_OUT
Y_OUT
C_OUT
V_REF_YC
I_REF_YC
V_GND_1
V_VCC_1
R_OUT
G_OUT
B_OUT
V_REF_RGB
I_REF_RGB
V_GND_0
V_VCC_0
OSD_ENABLE
VC
LAM
P
_1
VC
LAM
P
_2
VC
LAM
P
_3
U30
KM416V1200CT
18
19
20
21
24
25
26
27
28
29
2
3
4
5
7
8
9
10
35
36
37
38
40
41
42
43
11
12
13
16
17
33
34
14
15
30
31
32
1
6
22
23
39
44
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC.
NC.
NC.
NC.
NC.
NC.
NC.
W
RAS
OE
UCAS
LCAS
VCC
VCC
VCC
VSS
VSS
VSS
L11
4.7uH
DCU1
IDCBOXHEADER20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
U31
KM416V1200CT
18
19
20
21
24
25
26
27
28
29
2
3
4
5
7
8
9
10
35
36
37
38
40
41
42
43
11
12
13
16
17
33
34
14
15
30
31
32
1
6
22
23
39
44
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC.
NC.
NC.
NC.
NC.
NC.
NC.
W
RAS
OE
UCAS
LCAS
VCC
VCC
VCC
VSS
VSS
VSS
RDCU1
DUMMY
R65
10K
SP1
DUMMY
R75
0
+
C100
220uF
R109
390
SP2
DUMMY
D8
DALC112S1
6
8
1
2
3
4
5
7
H
L
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
R81
9.1K
1%
D4
DALC112S1
6
8
1
2
3
4
5
7
H
L
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
R107
10K
JP4
MS6
1
2
3
4
5
6
1
2
3
4
5
6
R110
390
RDCU2
10K
C92
82pF
+
C62
DUMMY
R134
1K
R108
0
RESET1
DUMMY
C61
DUMMY
C73
DUMMY
R150
DUMMY
C74
82pF
L4
22uH
+
C72
47uF
C87
82pF
U29
AM29LV160B_T
29
31
33
35
38
40
42
44
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25
12
15
37
46
11
28
26
16
9
10
13
14
27
47
30
32
34
36
39
41
43
45
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RESET
RY/BY
VCC
VSS
WE
OE
CE
A18
A19
NC.
NC.
NC.
VSS
BYTE
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
R5
DUMMY
C85
DUMMY
C78
100nF
U28
AM29LV160B_T
29
31
33
35
38
40
42
44
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25
12
15
37
46
11
28
26
16
9
10
13
14
27
47
30
32
34
36
39
41
43
45
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RESET
RY/BY
VCC
VSS
WE
OE
CE
A18
A19
NC.
NC.
NC.
VSS
BYTE
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
L3
DUMMY
R67
4.7K
L9
4.7uH
R112
39
C77
100nF
R111
39
C90
82pF
R90
9.1K
1%
R92
390
R106
39
L5
4.7uH
C52
100nF
R113
39
C88
DUMMY
C75
82pF
H1
DUMMY
2
1
R114
10K
R78
DUMMY
R93
390
R105
39
R115
10K
R102
39
L10
4.7uH
L6
22uH
X1
27MHz
1
4
3
2
V CONT
VCC
OUT
GND
R69
39
H2
DUMMY
2
1
C86
82pF
R98
39
C81
82pF
+
C79
220uF
R140
0
R71
39
U25
CS4330-KS
2
3
4
7
6
8
1
5
notDEM/SCLK
LRCK
MCLK
VA+
AGN
D
AOUTL
SDATA
AOUTR
R103
390
BS1
0
C76
DUMMY
TSCA_D[0..7]
3
TSCA_START
3
TSCA_VALID
3
TSCA_CLK
3
Vpp A
9
Card det B
9
Vpp B
9
Vpp low
9
Card I/O A
9
Card det A
9
Card Clock B
9
Card Reset B
9
-Power A
9
Card Reset A
9
Card I/O B
9
-Power B
9
Card Clock A
9
/INT0
3
I2CSCL
4,5,8
I2CSDA
4,5,8
-RESET3.3V 4
CLK 27MHZ
3
DIG-AUD-L 8
DIG-AUD-R 8
IR RX SCART
8
FBL
8
RDIG
8
GDIG
8
BDIG
8
YDIG
8
CDIG
8
CVBSDIG 8
/D_WAIT
3
D_RD/WR
3
/D_CS2
3
/D_BE2
3
/D_BE3
3
DD[0..7]
3
DA[2..23]
3
SCTX
8
SCRX
8
/RESET5V 3
50HZ
7
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
32:(5
Thursday, January 20, 2000
A4
1030-00003-4
1.0
Power Section
9
7
Date:
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing is copyright of
FORCE Electronics A/S Denmark.
Legal actions will be taken against any company using or
copying the design/ideas or information contained on this
drawing without prior written permission.
5V
22V
30V
3.3V
12V
JP7
POWER PINHEADER
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
50HZ
6
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
BLUE
GREEN
RED
9&
5
'(
&2
'(
5
79
6&$57
B&O
Thursday, Ja nuary 20, 2000
A2
1030-00003-4
1.0
SCART & Modulator
9
8
Date :
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing is copyr
ight of
FORCE Electronics A/S Denmar k.
Legal actions will be taken against any company using
or
copying the design/ideas or information contained on
this
drawing without prior written permission
.
BM
MACORDIG
AUD-VCR-OUT R
AUD-VCR-IN L
TVScartPin8
CVBSOUTSW
COUTSW
YOUTSW
BUB
GUB
RUB
FBLUB
SW-FNC-OUT
RG
B
O
U
T
G
RG
B
O
U
T
B
RG
B
O
U
T
R
C
VBS O
U
T
FB
L
O
U
T
VCR-G -IN
VCR-CVBS-IN
VCR-CVBS-OUT
VCR-B-IN
VCR-FNC- IN
TV-AUD-IN R
TV-AUD-IN L
AUD-DEC-IN L
AUD-VCR-IN L
AUD-VCR- IN R
MONO AUDIO
TV-AUD-OUT R
TV-AUD-OUT L
AUD-VCR-OUT R
AUD-VCR-OUT L
DEC-VID IN
AUD-DEC-OUT R
AUD-DEC- IN R
AUD-DEC-OUT L
DEC-R IN
DEC-B IN
DEC-G IN
VCR-B-IN
AUD-DEC-IN L
DEC-FB IN
DEC-FCN I N
DEC-VID OUT
DEC-FCN I N
VCR-CVBS-IN
PHONO R
PHONO L
9V
VCR-FBL-IN
VCR-R/C- IN
VCR-G -IN
VCR-FBL-IN
MONO AUDIO
I2CSCL
I2CSDA
PHONO R
PHONO L
DEC-VID IN
AUD-DEC-OUT L
AUD-DEC- IN R
AUD-DEC-OUT R
DEC-B IN
DEC-R I N
DEC-FB IN
DEC-G IN
TV-AUD-OUT R
TV-AUD-IN R
TV-AUD-OUT L
TV-AUD-IN L
AUD-VCR- IN R
AUD-VCR-OUT L
VCR-FNC-IN
GM
RM
CVBSUB
CVBSUB
CVBSMOD
12V
9V
12V
9V
12V
9V
9V
9V
9V
5V
5V
5V
30V
12V
12V
12V
12V
12V
I2CSDA
I2CSCL
C106
470nF
+
C32
47uF
C110
470nF
Q11
BC847
1
2
3
C21
4.7 nF
C111
470nF
Q12
BC847
1
2
3
Q13
BC847
1
2
3
Q3
BC847
1
2
3
Q14
BC847
1
2
3
Q15
BC847
1
2
3
D1
1N4148
R28
1K
R33
1K
R9
1K
R34
1K
Q7
BC847
1
2
3
R151
DUMMY
R26
75
R10
2.2 K
R30
75
R152
DUMMY
R35
75
R15
1K
R31
22K
R153
DUMMY
J2
IDCBOXHEADER40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R32
15K
R18
1K
J3
IDCBOXHEADER40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R154
DUMMY
R23
100
R12
1K
R128
10K
R155
DUMMY
R13
220
R156
DUMMY
R20
22K
R21
1K
R14
100K
+
C33
22uF
R22
1K
R24
1K
R11
2.2K
R25
1K
R27
1K
U17
4053
12
13
3
4
2
1
5
9
6
11
10
14
15
16
8
7
X0
X1
Z1
Z
Y0
Y1
Z0
C
INH
A
B
X
Y
VDD
VSS
VEE
Q16
BC847
1
2
3
R148
DUMMY
R129
DUMMY
+
C34
2.2 uF
+
C23
1uF
R8
4.7 K
R130
DUMMY
+
C35
2.2 uF
R17
1K
R36
1K
Q4
BC857
2
3
1
+
C28
10u F
VIDEO
AUDIO
I2C
DIG
VCR
AUX
TV
SAT
DIG
VCR
AUX
TV
SAT
TV
VCR
AUX
TV
VCR
AUX
U18
CXA2125Q
52
53
51
63
61
13
2
59
15
4
6
57
8
10
55
21
23
25
60
62
7
20
19
26
38
43
58
56
54
3
12
16
22
27
5
14
18
17
24
29
45
64
1
11
9
50
48
47
46
49
41
44
39
33
35
37
40
42
34
36
31
32
30
28
FBLK_IN1
FBLK_IN2
FBLK_IN3
Vin1 B
Vin2 B
Vin3 B
Vin4 G
Vin5 G
Vin6 G
Vin7 R
Vin8 C
Vin9 R/C
Vin11 CVBS
Vin12 Y
Vin13-CVBS/Y
Vin14-CVBS/Y
Vin15-CVBS
Vin16-CVBS
VID_VCC
VID_BIAS
VID_GND
AUD_VCC
AUD_BIAS
AUD_GND
DIG_VCC
DIG_GND
VCC_12V
VREG_BASE
VREG_9V
Rin1
Rin2
Rin3
Rin4
Rin5
Lin1
Lin2
Lin3
Vin10 R/C
Lin4
Lin5
HW_MUTE
FNC_VCR
FNC_AUX
SDA
SCL
FBLANK
VOUT1 B
VOUT2 G
VOUT3 R
VOUT4 CVBS
VOUT5 C
VOUT6 CVBS/Y
VOUT7 CVBS
MONO
PHONO_R
PHONO_L
RTV
LTV
ROUT1
LOUT1
ROUT2
LOUT2
FNC
LOGIC
R29
75
Q2
BC847
1
2
3
C29
100nF
+
C26
10uF
+
C25
1uF
C27
100nF
C31
100nF
D2
1N4148
Q8
BC847
1
2
3
U19
4053
12
13
3
4
2
1
5
9
6
11
10
14
15
16
8
7
X0
X1
Z1
Z
Y0
Y1
Z0
C
INH
A
B
X
Y
VDD
VSS
VEE
+
C30
10uF
R16
100K
Q5
BC847
1
2
3
Q10
BC847
1
2
3
Q6
BC847
1
2
3
C108
470nF
R19
220
C109
470nF
Q9
BC847
1
2
3
C107
470nF
GOUT
5
BOUT
5
RDIG
6
GDIG
6
BDIG
6
FBL
6
MACPAL
5
MACYOUT
5
MACCOUT
5
CVBSDIG
6
YDIG
6
CDIG
6
I2CSCL
4,5 ,6
I2CSDA
4,5 ,6
IR RX SCART 6
DIG- AUD-L
6
DIG-A UD-R
6
MacLef tAudio
5
MacRightAudio
5
ROUT
5
SCTX
6
SCRX
6
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
CARD A
CARD B
Vpp = 15V or 5V.
&$5'5($'(5
Vpp
I/O
GND
clk
Res
Vcc
GND
Vpp
I/O
GND
clk
Res
Vcc
GND
ID B
ID A
Thursday, Ja nuary 20, 2000
A2
1030-00003-4
1.0
Smart Card Re ader If.
9
9
Date :
Sheet
of
Size
Document Number
Rev
Title
All information contained on this drawing is copyr
ight of
FORCE Electronics A/S Denmar k.
Legal actions will be taken against any company using
or
copying the design/ideas or information contained on
this
drawing without prior written permission
.
Card Re set B
Vpp low
Vpp
Vcc_A
Vpp_B
Vpp_B
Vcc_B
Vpp A
Vpp B
Vpp
Vpp
-Power B
-Power A
conRESA
Card Re set A
conIOB
conCLKB
conRESB
Det B
conIOA
conCLKA
Card I/ O A
Clock A
Card I/ O B
Card Clo ck B
Det A
Vpp_A
Vpp_A
5V
5V
Vcc_A
Vcc_A
Vcc_B
22V
Vcc_B
5V
5V
5V
Q19
BC857
2
3
1
R39
4.7K
Q18
BC857
2
3
1
Q20
BC847
1
2
3
R38
100K
R40
100K
Q21
BC857
2
3
1
Q22
BC857
2
3
1
R137
10K
J4
IDCBOXHEADER16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R138
10K
R42
10K
C39
100nF
C38
100nF
C36
100nF
C37
100nF
D3
DALC112S1
6
8
1
2
3
4
5
7
H
L
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
U20
LM317LD
1
2
4
3
6
7
5
8
Input
Output
Adjustment
Output
Output
Output
NC
NC
R37
301
1%
R52
10K
R41
909
1%
Q23
BC847
1
2
3
R54
10K
R44
10K
5%
R53
100
R45
2.43K
1%
R51
100
R48
4.7K
R50
10K
R49
4.7 K
Q24
BC847
1
2
3
R46
100K
R47
100K
R43
4.7 K
-Power A
6
-Power B
6
Vpp A
6
Vpp B
6
Card Re set B
6
Card d et A
6
Card d et B
6
Vpp low
6
Card I/ O B
6
Card Cl ock B
6
Card I /O A
6
Card Cl ock A
6
Card Re set A
6
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