Podstawy techniki

mikroprocesorowej

ETEW006

Grupy rozkazów, dekodowanie

i wykonywanie rozkazów,

tryby adresowania

Andrzej Stępień

Katedra Metrologii Elektronicznej i Fotonicznej

Linia kodu programu

[etykieta:]

[; komentarz]

etykieta

- symboliczny adres,

instrukcja

- rozkaz wykonywany przez procesor,

mnemonik

- symboliczna nazwa instrukcji,

operand

- argumenty instrukcji,

dyrektywa

- polecenie dla asemblera,

komentarz

- tekst pomijany przez asembler, od ‘;’ do CR LF

mnemonik instrukcji

[operand1], [operand2], ..

dyrektywa

instrukcja

MU0

Simple Processor

• program counter

(

PC

) register -

used to hold the address of the
current instruction

• accumulator

(

ACC

) - single

register, holds a data value while
it is worked upon

• arithmetic-logic unit

(

ALU

) -

perform a number of operations
on binary operands, such as add,
subtract, increment, and so on

• instruction register

(

IR

) - holds

the current instruction while it is
executed

• instruction

decode

and

control

logic

that employs the above

components to achieve the
desired results from each
instruction

PC

IR

ACC

Bsel

ACC[15]

ACCz

ALUfs

ACCce

MU0

memory

MEMrq

RnW

IRce

opcode

PCce

Asel

ACCoe

ALU A

B

m

u

x

0

1

mux

0

1

Figure 1.6

Steve Furber: ARM System-on-Chip Architecture.

2nd Edition. Addison Wesley, 2001, ISBN-10: 0-201-67519-6

MU0

Basic

Components

MU0

is a

16-bit machine

with a

12-bit address space

, so it can address up

to 8 Kbytes of memory arranged as 4,096 individually addressable 16-bit
locations.

Instructions are 16 bits long

, with a

4-bit operation code (or opcode)

and

a 12-bit address field (S). The simplest instruction set uses only eight of the
16 available opcodes.

An

instruction

such as

'ACC := ACC + mem

16

[S]'

means

'add

the

contents

of

the (16-bit wide)

memory

location whose

address

is

S to

the

accumulator'

. Instructions are fetched from consecutive memory addresses,

starting from address zero, until an instruction which modifies the PC is
executed, whereupon fetching starts from the new address given in the 'jump'
instruction.

Instruction

Opcode

Effect

LDA

S

0000

ACC := mem

16

[S]

STO

S

0001

mem

16

[S] := ACC

ADD S

0010

ACC := ACC + mem

16

[S]

SUB

S

0011

ACC := ACC – mem

16

[S]

JMP

S

0100

PC := S

JGE

S

0101

if ACC

≥

0 PC := S

JNE

S

0110

if ACC

≠

0 PC := S

STP

0111

stop

opcode

S (memory address)

4 bits

12 bits

MU0 - Instruction set design

basic machine operation such as an instruction to

add two numbers

to

produce a

result

most general form:

– instruction requires some

bits to differentiate

it from other

instructions

,

– some

bits

to

specify

the

operand addresses

,

– some

bits

to

specify where

the

result

should be placed (

destination

),

– and some

bits

to specify the

address

of the

next instruction

to be

executed

4/3/2/1/0 - address instructions format

4 / 3 - address instructions format

4-address instructions format

:

ADD

d, s1, s2, next_i

; d := s1 + s2
; format requires 4n + f bits per instruction

function

op 1 addr

op 2 addr

dest addr

next_i addr

f bits

n bits

n bits

n bits

n bits

3-address instruction format

(reduce the number of bits required for

each instruction is to make the address of the next instruction implicit - if
we assume that the default next instruction can be found by adding the
size of the instruction to the PC:

ADD

d, s1, s2

; d := s1 + s2
; format requires 3n + f bits per instruction

function

op 1 addr

op 2 addr

dest addr

f bits

n bits

n bits

n bits

2 / 1 / 0 - address instructions format

function

op 1 addr

dest addr

f bits

n bits

2-address instructions format

- saving in the number of bits required

to store an instruction can be achieved by making the destination
register the same as one of the source registers:

ADD

d, s1

; d := d + s1

function

op 1 addr

dest addr

n bits

1-address instructions format

- if the destination register is made

implicit it is often called the

accumulator

:

ADD

s1

; acc := acc + s1

function

op 1 addr

f bits

n bits

function

op 1 addr

0-address instructions format

- an architecture may make all operand

references implicit by using an evaluation stack:

ADD

; top_of_stack := top_of_stack + next_on_stack

function

f bits

function

Interruption management

RETI

Unconditional Jump or Call

ACALL, LCALL, RET

Conditional Branch

JZ, JNZ, JC, JNC, JB, JNB, JBC,
CJNE, DJNZ

Logical operations

ANL, ORL, XRL, CLR, CPL

Bit Operation

CLR, SETB, CPL, ANL, ORL, MOV

Shift and Rotates

RL, RLC, RR, RRC, SWAP

Arithmetic operations

ADD, ADDC, SUBB, MUL, DIV, DA

Increment/Decrement

INC, DEC

Load and Transfer

MOV, MOVC, MOVX, XCH, XCHD

Stack operation

PUSH, POP

C51 Instruction Set

(111 Instructions)

data
transfer

arithme-

tic

logic

control

transfer

MCU control

NOP

UM10344. P89LPC9151/9161/9171 User manual.

NXP Semiconductors, 7 January 2010, Rev. 01, p.128-130

Interruption management

TRAP, WFI, HALT, IRET

Unconditional Jump or Call

JRA, JRT, JRF, JP, CALL, CALLR, RET

Conditional Branch

JRxx

Conditional Bit Test and Branch

BTJT, BTJF

Logical operations

AND, OR, XOR, CPL, NEG

Shift and Rotates

SLL, SRL, SRA, RLC, RRC, SWAP, SLA

Bit Operation

BSET, BRES

Tests

TNZ, BCP

Code Condition Flag modification

SIM, RIM, SCF, RCF

Arithmetic operations

ADC, ADD, SUB, SBC, MUL

Increment/Decrement

INC, DEC

Compare

CP

Load and Transfer

LD, CLR

Stack operation

PUSH, POP, RSP

C51 Instruction Set (111 Instructions)

ST7 Instruction Set

(63 Instructions)

ST7 FAMILY. PROGRAMMING MANUAL.

STMicroelectronics, November 2005, p.30

data transfer

arithmetic

logic

control transfer

MCU control NOP

Interruption management

RETI

Unconditional Jump or Call

JMP, CALL

Conditional Branch

JEQ/JZ, JNE/JNZ,
JC, JNC, JN, JGE, JL

Conditional Bit Test and Branch

BTJT, BTJF

Logical /Bit operations

BIT, BIC, BIS, XOR

Shift and Rotates

RRC, RRA, SWPB

Arithmetic operations

ADD, ADDC, SUB, SUBC,
DADD, SXT

Increment/Decrement

INC, DEC

Compare and Tests

CMP

Load and Transfer

MOV

Stack operation

PUSH

C51 Instruction Set (111 Instructions)
ST7 Instruction Set (63 Instructions)

MSP430 Core Instruction Set

(27 Instructions)

MSP430x4xx Family. User’s Guide.

Texas Instruments 2007, SLAU056G p.3-17

data transfer

arithmetic

logic

control transfer

Load and Transfer

MOV, MOVW, LDI, LD, LDD, LDS,
CLR, SET, ST, STD, STS, LPM, SPM,
IN, OUT

Stack operation

PUSH, POP

C51 Instruction Set (111 Instructions)

ST7 Instruction Set (63 Instructions)

MSP430 Core Instruction Set (27 Instructions)

ATmega32 Instruction Set

(132 Instructions) 1/2

ATmega32A. 8-bit Microcontroller with 32K Bytes In-System

Programmable Flash. Atmel, 8155A–AVR–06/08, p.336

data
transfer

MCU control

NOP, SLEEP, WDR, BREAK

Logical operations

AND, ANDI, OR, ORI, EOR,
COM, NEG

Shift and Rotates

LSL, LSR, ROL, ROR, ASR, SWAP

Bit operations

BSET, SBI, SBR, BCLR, CBI, CBR,
BST, BLD, SEC, CLC, SEN, CLN,
SEZ, CLZ, SES, CLS, SEV, CLV,
SET, CLT, SEH, CLH

logic

Interruption management

SIE, CLI, RETI, BRIE, BRID

Unconditional Jump or Call

RJMP, IJMP, JMP,
RCALL, ICALL, CALL, RET

Conditional Branch

BRBC, BREQ, BRNE,
BRCS, BRCC, BRSH, BRLO, BRMI,
BRPL, BRGE, BRLT, BRHS, BRHC,
BRTS, BRTC, BRVS, BRVC

Conditional Bit Test and Branch

SBRC, SBRS, SBIC, SBIS, BRBS

C51 Instruction Set (111 Instructions)

ST7 Instruction Set (63 Instructions)

MSP430 Core Instruction Set (27 Instructions)

ATmega32 Instruction Set

(132 Instructions) 2/2

ATmega32A. 8-bit Microcontroller with 32K Bytes In-System

Programmable Flash. Atmel, 8155A–AVR–06/08, p.336

control

transfer

Arithmetic operations

ADD, ADC, ADIW,
SUB, SUBI, SBC, SBCI, SBIW,
MUL, MULS, MULSU, FMUL,
FMULS, FMULSU

Increment/Decrement

INC, DEC

Compare and Tests

TST, CPSE, CP, CPC, CPI

arithmetic

C51

Logical Operations

ANL

arg_1, arg_2

; arg_1

←

arg_1 AND arg_2

ORL

arg_1, arg_2

; arg_1

←

arg_1 OR arg_2

XRL

arg_1, arg_2

; arg_1

←

arg_1 XOR arg_2

CPL

A

; A

←

NOT A

SWAP

A

; Swap Nibbles of A

RL

A

; Rotate A left

RLC

A

; Rotate A left through carry

RR

A

; Rotate A right

RRC

A

; Rotate A right through carry

A

7

A

0

A

7

A

0

A

7

A

0

C

A

7

A

0

C

A

7

..A

4

A

3

..A

0

1, 2 Cycles

(Standard)

UM10344. P89LPC9151/9161/9171 User manual.

NXP Semiconductors, 7 January 2010, Rev. 01, p/128-129

Maskowanie bitów

wyzerowa

ć

podane bity akumulatora A: A

6

, A

5

, A

2

i A

0

.

Zerowanie_bitów:

ANL

A, #

NOT Maska

; A

←

A

AND NOT

maska

Ustawianie_bitow

:

ORL

A, #

Maska

; A

←

A

OR

maska

Negacja_bitow

:

XRL

A, #

Maska

; A

←

A

XOR

maska

Maska

EQU

0110 0101b

7

6

5

4

3

2

1

0

akumulator A:

; deklaracja bitów maski

0

1

1

0

0

1

0

1

;

maska

:

MSP430 - Logical Operations

AND

(.B)

src,dst

; src .and. dst

→

dst

BIT

(.B)

src,dst

; src .and. dst

BIC

(.B)

src,dst

; .not.src .and. dst

→

dst

BIS

(.B)

src,dst

; src .or. dst

→

dst

XOR

(.B)

src,dst

; src .xor. dst

→

dst

*

INV

[.B]

dst

; .NOT.dst

→

dst

; Invert destination,

Emulation

XOR #0FFFFh,dst

SWPB

dst

Swap bytes

SXT

dst

Bit 7

→

Bit 8........Bit 15

*RLA

(.B) dst

; C

←

MSB

←

MSB−1 .... LSB+1

←

LSB

←

0

; Rotate left arithmetically,

Emulation

ADD dst,dst

*RLC

(.B) dst

; C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C
; Rotate left through carry,

Emulation

ADDC dst,dst

RRA

(.B)

dst

MSB

→

MSB

→

....LSB

→

C

RRC

(.B)

dst

C

→

MSB

→

.......LSB

→

C

Shift operations

(1/2)

N

0

K

K-1

N

0

K K-1

Before:

After:

MSP430: SXT dst

Extend sign, the
sign of the LOW byte
is extended into the
HIGH byte

N

0

K

K-1

N

0

K

K-1

Before:

After:

C51

ST7

MSP430

SWAP A

SRA reg [mem]

SWPB dst

Shift operations

(2/2)

C51

ST7

MS430

RR

A

???

???

???

SRL

reg [mem]

???

RRC A

RRC reg [mem]

RRC dst

???

SRA reg [mem]

RRA dst

C

dst

N

→

...

→

dst

0

C

0

N

dst

N

→

...

→

dst

0

0

N

dst

N

→

...

→

dst

0

0

N

dst

N

→

...

→

dst

0

0

N

C

0

C51: Wielobajtowe przesuwanie bitów

przesun

ąć

binarnie (podzieli

ć

przez 2) 2-bajtow

ą

zmienn

ą

zawart

ą

w rejestrach: R7 (MSB) i R6 (LSB).

Przesun_2_bajty:

MOV

A, R7

; A

←

R7

RRC

A

; C

→

A

7

→

A

6

.. A

1

→

A

0

→

C

MOV

R7, A

; R7

←

A

MOV

A, R6

; A

←

R6

RRC

A

; C

→

A

7

→

A

6

.. A

1

→

A

0

→

C

MOV

R6, A

; R6

←

A

7

6

5

4

3

2

1

0

R7:

przykład:

7

6

5

4

3

2

1

0

R6:

C

C = ?

C

ARM7

Logical Operations

AND

Rd := Rn

AND

shifter_operand

TST

ONLY Update flags

after Rn

AND

shifter_operand Test

BIC

Rd := Rn

AND NOT

(shifter_operand)

Bit Clear

ORR

Rd := Rn

OR

shifter_operand

EOR

Rd := Rn

EOR

shifter_operand

Exclusive OR

TEQ

ONLY Update flags

after Rn

EOR

shifter_operand Test Equivalence

Example:
j = 0x12345678;

LDR

R0, [PC, #0x0074]

; R0 = 0x1234 5678

j = (j >> 4) & 0x3FF;

LDR

R1, [PC, #0x0074]

; R1 = 0x0000 03FF

AND R0, R1, R0, ASR #4

; R0 = 0x0000 0167

ARM7

Barrel shifter

(1/2)

mult

A[31:0]

control

Data out register

Data in register

Instruction

decode

&

control

A

L

U

b
u

s

B

b
u

s

A

b
u

s

Barrel

shifter

ALU

P

C

Register

bank

P

C

incrementer

Address register

ability to

shift

the 32-bit binary

pattern in one source registers
left or right by a specific number
of positions before it enters the
ALU

shifting

increases the power and

flexibility of many data processing
operations

5

different

shift

operations:

logical shift left

LSL

logical shift right

LSR

arithmetic shift right

ASR

rotate right

ROR

rotate right extended

RRX

ARM7

5 different shift operations

destination

0

LSL - L

ogical

S

hift

L

eft by n bits

(multiplication by 2

n

)

LSR - L

ogical

S

hift

R

ight

by n bits

(unsigned division by 2

n

)

CF

ASR - A

rithmetic

S

hift

R

ight

by n bits; the

bits fed into the top end of the operand are
copies of the original top-or sign-bit
(signed division by 2

n

)

0

ROR - RO

tate

R

ight

by n bits

CF

destination

CF

destination

CF

destination

RRX - R

otate

R

ight e

X

tended

only

by 1 bit

CF

destination

ARM7

Barrel shifter

no shift

in[3]

in[2]

in[1]

in[0]

out[0] out[1]

out[2] out[3]

right 1

right 2

right 3

left 1

left 2

left 3

principle of the cross-bar switch - 4 x 4 matrix,

Barrel

shifter

ALU

Steve Furber: ARM System-on-chip Architecture. p92

ARM use a 32 x 32 matrix

each switch is a single NMOS
transistor

each input is connected to each
output through a switch

- if pre-

charged dynamic logic is used, as
it is on the ARM datapaths

shifting functions

are

implemented by wiring

switches

along

diagonals

to a common

control input

ARM7

Left or right shift

out[0] out[1]

out[2] out[3]

no shift

right 1

right 2

right 3

left 1

left 2

left 3

for a

left

or

right

shift

function, one diagonal is
turned on

this connects all the input
bits to their respective
outputs where they are used

not all are used, since some
bits 'fall off the end‘

in the ARM the barrel shifter
operates in negative logic
where a ' 1' is represented as
a potential near ground and a
'0' by a potential near the
supply -

precharging sets all

the outputs to a logic '0'

, so

those

outputs that are not

connected to any input

in[3] = 1

in[2] = 1

in[1] = 0

in[0] = 0

in[3..0] = 1100

shift left 1

↔

↔

↔

↔

out[3..0] = 100

0

shift right 1

↔

↔

↔

↔

out[3..0] =

0

110

Format instrukcji - C51

(1/3)

kod rozkazu bez argumentów lub z pojedynczym, ukrytym argumentem:

0 0 0 0

0 0 0 0

np. NOP

1 1 1 0

0 1 1

i

kod rozkazu i argumenty:

→

1 bit dla adresowania po

ś

redniego:

np. MOV A, @Ri

1 0 0 1

0 0 1 1

np. MOVC A, @A+DPTR

→

3 bity dla adresowania rejestrowego:

1 1 1 0

1

r

r

r

np. MOV A, Rn

rozkazy 1- bajtowe

, 2-bajtowe i 3-bajtowe

Format instrukcji - C51

(2/3)

kod rozkazu i argumenty:

→

2 bajty dla adresowania bezpo

ś

redniego:

1 1 1 1

0 1 0 1

np. MOV addr, A

addr

1 0 1 1

0 1 0 1

np. CJNE A, addr, rel

→

3 bajty dla dwóch 1-bajtowych argumentów:

addr

rel

rozkazy

1-bajtowe,

2- bajtowe

i

3- bajtowe

Format instrukcji - C51

(3/3)

0 0 0 1

0 0 1 0

kod rozkazu i argumenty:

→

3 bajty dla jednego, 2-bajtowego argumentu:

np. CALL addr_16

addr_16

15..8

addr_16

7..0

Format rozkazu wykorzystuj

ą

cy ró

ż

ne podane kombinacje:

1 0 1 1

1

r r r

data

rel

np. CJNE Rn, #data, rel

rozkazy

1-bajtowe, 2-bajtowe i

3-bajtowe

PREFIX w kodach rozkazów C51

0x

NOP

x0

AJMP

addr11

x1

LJMP

addr16

x2

RR

A

x3

1x

OPCODE

PREFIX

JBC

bit, rel

ACALL

addr11

LCALL

addr16

RRC

A

2x

JB

bit, rel

AJMP

addr11

RET

RL

A

Ax

ORL

C, /bit

AJMP

addr11

MOV

C, bit

INC

DPTR

Dx

POP

addr

ACALL

addr11

LJMP

addr16

RR

A

Ex

MOVX

A,@DPTR

AJMP

addr11

MOVX

A, @Ri

Fx

MOVX

@DPTR,A

ACALL

addr11

MOVX

@Ri, A

INC

addr

x5

DEC

addr

ADD

A, addr

DJNZ

addr, rel

MOV

A, addr

MOV

addr, A

OPCODE
PREFIX = 0A5h
dodatkowe
instrukcje np.

80C51MX

(Philips)

C251

(Intel/Atmel)

Brak
instrukcji:

dla CODE
do 2KB

bez P0 i P2

Format instrukcji - PIC

16C77x (Microchip Techn.)

stała długo

ść

instrukcji równa 14-bitów

Byte-
oriented

file register
operations:

d = 0 for destination W (Working register - accumulator)
d = 1 for destination f (register file address: 0 .. 7Fh)

f = 7-bit file register address (0 .. 7Fh)

Bit-oriented

file register
operations:

OP-Code

d

f (FILE #)

0

6

7

8

13

b (BIT #)

f (FILE #)

0

6

10

9

13

7

OP-Code

b = 3-bit address (bit address within an 8-bit file register)

f = 7-bit register address (0 .. 7Fh)

CALL

and

GOTO

instructions

0

10

11

13

k (literal)

OP-Code

k = 11-bit immediate value (label

≡

address)

Procesory RISC
MSP430 — formaty rozkazów

dest. register

0

3

B/W

As

Ad

source register

OP - Code

6

7

5

4

8

11

12

15

Format I

dest. register

0

3

B/W

Ad

0

0

0

1

OP - Code

6

7

5

4

11

12

15

Format II

Offset

0

0

0

1

OP - Code

8

10

12

15

S

9

13

Format III

As

/

Ad

Addressing Mode

Contitional and unconditional Jumps (+/– 9 bit Offset)

Ad Addressing Mode

MSP430x4xx Family User’s Guide.

Texas Instruments, SLAU056G, 2007, p.3-18

ARM7

Instruction Set

ARM7DI Data Sheet. ARM DDI 0027D, Dec 1994, p.25

N

Z

C

31

28

V

0

CPSR / SPSR

Addressing Modes

C500

. Architecture and Instruction Set. User’s MANUAL.

Infineon, July 200, p.4-1

ST7 FAMILY PROGRAMMING MANUAL

.

STMicroelectronics, November 2005

MSP430x1xx Family User’s Guide. Texas Instruments, SLAU049F, 2006

8-bit AVR Instruction Set. Atmel, Rev. 0856G–AVR–07/08

ARM Architecture Reference Manual

.

ARM DDI 0100E, June 2000

Addressing Modes
Immediate

(1/2)

allows constants to be part of the instruction in program memory:

ANL

P1,

#01110011B

;

C51

:

P1

←

P1 and 01110011b

; clear bits 7, 3, and 2 of output port P1

add

A,

#$15

;

ST7

:

A

←

A + $15

ldi

r17,

0xFF

;

AVR

:

R17

←

0FFh

dadd.w

#0x9876

, R5

;

MSP430

: 9876h + R5 + C

→

R5

;

(

decimally)

SWI{<cond>} <

immed_24

> ;

ARM7

:

SWI (Software Interrupt)

; value <immed_24> is ignored by the ARM processor,
; but can be used by an operating system SWI exception
; handler to determine what operating system service is
; being requested

Addressing Modes
Immediate

(2/2)

allows constants to be part of the instruction in program memory:

ANL

P1

,

#01110011B

; P1

←

P1 and 01110011b

; clear bits 7, 3, and 2 of output port P1

0101 0011

1001 0000

0111 0011

P1 = 90h = 1001 0000

addr + 1

Constant = 73h

OpCode = 53h

addr + 2

addr

...........

...........

and

x x x x

x x x x

P1

0

7

0 1 1 1

0 0 1 1

2

3

Constant

0

x x x

0 0

x x

P1

Program

Memory

...........

addr + 3
addr + 4

addr – 1

C500. Architecture and Instruction Set. User’s MANUAL.

Infineon, July 2000, p.4-18

Addressing Modes
Register

accesses the working registers

:

ANL

B

,

#01110011B

;

C51

:

B

←

B and 01110011b

add

A

,

#$15

;

ST7

:

A

←

A + $15

ldi

r17

,

0xFF

;

AVR

:

R17

←

0FFh

dadd.w

#0x9876

,

R5

;

MSP430

: 9876h + R5 + C

→

R5

;

(

decimally)

MOV

R2

,

R0

, LSL #2

;

ARM7

:

Shift R0 left by 2, write to R2

;

(R2 = R0

∗

4)

C51 Addressing Modes
Register

C500. Architecture and Instruction Set. User’s MANUAL.

Infineon, July 200, p.4-1

accesses the eight working
registers (R0 - R7) of the
selected register bank —
least significant bit of the
instruction opcode indicates
which register is to be used.
ACC, B, DPTR and CY, the
Boolean processor
accumulator, can also be
addressed as registers

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

temp

ALU

A

PSW

C51 Core

B

DPTR

R0

R1

R2

R3

R4

R5

R6

R7

RB0

RAM

7Fh

80h

0FFh

0

RB1

RB2

RB3

1Fh

0

0xxh

256-byte

100h

256-byte

200h

256-byte

300h

external

RAM

SFR

RAM

Addressing Modes
Direct

address is a byte or word, thus require only one byte or word after the
op-code:

ANL

P1

,

#01110011B

;

C51

:

(P1)

←

(P1) and 01110011b

ld

A,

$4B

;

ST7

:

A

←

($4B)

lds

r12,

0x00FF

;

AVR

:

R12

←

(00FFh)

; MSP430 ;

LDR

PC, Reset_Addr

; ARM7

:

PC

←

(Reset_Addr)

only

method of

accessing

the special function registers

SFR

lower 128 bytes of internal
RAM

C51 Addressing Modes
Direct

C500. Architecture and Instruction Set. User’s MANUAL.

Infineon, July 200, p.4-1

temp

ALU

A

PSW

C51 Core

B

80h

0FFh

0

0xxh

256-byte

100h

256-byte

200h

256-byte

300h

external

RAM

RAM

SFR

RB0

RAM

7Fh

0

RB1

RB2

RB3

1Fh

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

DPTR

R0

R1

R2

R3

R4

R5

R6

R7

ST7 Addressing Modes
Short / Long Direct

allows constants to be part of the instruction in program memory:

LDA

A,

$4B

; A

←

($4B),

; Short Direct, 0..FF addressing space

LDA

A,

$06E5

; A

←

($06E5),

; Long Direct, 0..FFFF addressing space

$B6
$4B

addr + 1

Coeff addr

OpCode

addr + 2

addr

..........

..........

$20

$004B – 1

$004B

addr – 1

ST7 FAMILY PROGRAMMING MANUAL.

STMicroelectronics, November 2005, p.12-13

..........

Memory

..........

$004B + 1

..........

Coeff

$C6

$06

addr + 1

Coeff addr

OpCode

addr + 3

addr

..........

..........

$40

$06E5 – 1

$06E5

addr – 1

..........

Memory

..........

$06E5 + 1

..........

Coeff

$E5

addr + 2

A

A

Addressing Modes
Indirect

operand address is a register or pointer contens:

ADD

A,

@R1

;

C51

:

A

←

A + (R1), only R0, R1

cp

A,

[ptr]

;

ST7

:

Reg CC: {N, Z, C}

←

A – ((ptr))

ld

r10,

X

;

AVR

:

R10

←

(X),

; Loads one byte indirect from the data
; space (X or Y or Z) to a register Rd

cmp

@r6

, r7

;

MSP430

: Reg SR: {N, Z, C, V}

←

r7 – (r6)

STR

R3,

[R2]

;

ARM7

:

[R2]

←

R3,

; store word from R3 to the address in R2

uses contents of either

R0

or

R1

(in the selected

register bank)

R0

or

R1

is a

pointer

to

locations in a

256-byte

block internal of RAM

R0

or

R1

is a

pointer

to

locations in a

256-byte

block of external RAM
(256

∗∗∗∗

P2 + Ri)

C51 Addressing Modes
Indirect

C500. Architecture and Instruction Set. User’s MANUAL.

Infineon, July 200, p.4-1

temp

ALU

A

PSW

C51 Core

B

80h

0FFh

0

0xxh

256-byte

100h

256-byte

200h

256-byte

300h

external

RAM

RAM

SFR

RB0

RAM

7Fh

0

RB1

RB2

RB3

1Fh

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

R0

R1

R2

R3

R4

R5

R6

R7

DPTR

R0

R1

R2

R3

R4

R5

R6

R7

MSP430 Addressing Modes
Indirect and ???

indirect autoincrement

:

MOV.W

@R10+

, R11

; (R10)

→

R11

; R10 + 2

→

R10, post incremented

; Move the contents of the source address (contents of R10) to
; the destination register R11. Register R10 is incremented by
; 1 for a byte operation, or 2 for a word operation after the fetch;
; it points to the next address without any overhead – useful for
; table processing

MSP430x1xx Family User’s Guide.

Texas Instruments, SLAU049F, 2006, p.3-15

AVR Addressing Modes
Indirect and ???

loads one byte indirect with or without displacement from the data space
to a register

•

indirect post-autoincrement

LD

R13, Y+

; R13

←

(Y)

; Y

←

Y + 1,

post incremented

•

indirect pre-autodecrement

LD

R13, – Y

; Y

←

Y – 1,

pre decremented

; R13

←

(Y)

•

indirect with displacement

LD

R13, Y + 48

; R13

←

(Y + 48)

features are especially suited for accessing arrays, tables, and Stack
Pointer usage of the Y-pointer Register

8-bit AVR Instruction Set.

Atmel, Rev. 0856G–AVR–07/08, p.85

Addressing Modes
Indexed

MOVC A,

@A+DPTR

;

C51

:

A

←

(A + DPTR)

CODE

LD

A,

([ptr.w], X)

;

ST7

:

A

←

([ptr.word], X)

LD

Rd,

X

;

AVR:

Load Indirect from Data Space

LD

Rd,

X+

;

to Register using

Index X

LD

Rd,

–X

MOV

2(R5), 6(R6)

;

MSP430

: (2 + (R5))

→

(6 + (R6))

LDRcc R0,

[R1, #12] !

;

ARM7

:

if cc = true then R1 = R1 + 12

;

R0

←

(R1 + 12),

pre-indexed

LDRcc R0,

[R1], #12

;

ARM7

:

R0

←

(R1),

post-indexed

;

if cc = true then R1 = R1 + 12

ST7 Addressing Modes
Indirect indexed

loads one byte indirect with or without displacement from the data space to a
register

•

Short /

Long indirect indexed

(

pointer address is a byte

, the pointer size is a byte / word)

LD

A, ([ptr.w], X)

; A

←

([ptr.word], X)

Example

:

0089

0800

ptr

dc.wtable

0800

102030

40

table

dc.b$10,$20,$30,

$40

0690

AE

03

ld

X,

#3

;

X = 3

0692

92D6

89

ld

A, ([

ptr.w

],

X

)

; A

←

([

ptr.w

],

X

) =

;

((

$89.w

),

3

) =

;

(

$0800

,

3

) =

;

(

$0803

) =

;

$40

ST7 FAMILY PROGRAMMING MANUAL.

STMicroelectronics, November 2005, p.21-25

0800+3

1

2

4

3

1

2

3

4

MSP430 Addressing Modes
Indexed

MOV

#01080h, R5

; 01080h

→

R5

MOV

#0108Ch, R6

; 0108Ch

→

R6

MOV

2(R5),

6(R6)

; (

2 + (R5)

)

→

(

6 + (R6)

)

MSP430x1xx Family User’s Guide.

Texas Instruments, SLAU049F, 2006, p.3-11

00006h

00002h

0FF14h

0FF10h

..........

0FF18h

..........

Address

Space

04596h

0FF12h

0FF16h

PC

05555h

01092h

..........

..........

01090h

01094h

01234h

01082h

..........

..........

01080h

01084h

R6 = 0108Ch

+0006h

01092h

R5 = 01080h

+0002h

01082h

MSP430 Addressing Modes

Symbolic, Absolute

MOV

EDE

,

TONI

; MOV X(PC), Y(PC)
;

X = EDE − PC

,

;

Y = TONI − PC

; Src addr

EDE = 0F016h

; Dst addr

TONI = 01114h

011FEh

0F102h

0FF14h

0FF10h

..........

0FF18h

..........

Address

Space

04090h

0FF12h

0FF16h

0A123h

0F016h

..........

..........

0F014h

0F018h

05555h

01114h

..........

..........

01112h

01116h

0FF14h

+0F102h

0F016h

0FF16h

+011FEh

01114h

S

y

m

b

o

li

c

m

o

d

e

MOV

&EDE

,

&TONI

; MOV X(0),Y(0)
;

X = EDE

;

Y = TONI

; Src addr

EDE=0F016h

,

; Dst addr

TONI=01114h

A

b

s

o

lu

te

m

o

d

e

MSP430x1xx Family User’s Guide.

Texas Instruments, SLAU049F, 2006, p.3-12..13

Relative Addressing

Addressing Modes
Relative

DJNZ

Rn,

rel

;

C51

:

Rn

←

Rn – 1

;

if Rn = 0 then PC

←

PC + rel

JRcc

label

;

ST7

:

if (cc == 1) then

;

PC = PC + oft

;

or PC = PC + (oft)

;

else PC = PC

RJMP

k

;

AVR:

PC

←

PC + k + 1

;

–2K

≤

k < 2K

MOV

EDE

,

TONI

;

MSP430

: MOV X(PC), Y(PC)

;

X = EDE − PC

;

Y = TONI − PC

LDR

Rd,

=const

;

ARM7

:

LDR Rn, [PC, #offset to literal pool]

;

load Rn register with one word

;

from the address [PC + offset]

Memory Addressing Mode 2

Load and Store Word or Unsigned Byte

LDR|STR{<cond>}{B}{T} <Rd>,

<addressing_mode>

where

<addressing_mode>

is one of the nine options for Word or Unsigned

Byte:

[<Rn>, #+/-<offset_12>]

Immediate offset

[<Rn>, +/-<Rm>]

Register offset

[<Rn>, +/-<Rm>, <shift> #<shift_imm>]

Scaled register offset

[<Rn>, #+/-<offset_12>]

!

Immediate

pre-indexed

[<Rn>, +/-<Rm>]

!

Register

pre-indexed

[<Rn>, +/-<Rm>, <shift> #<shift_imm>]

!

Scaled register

pre-indexed

[

<Rn>

]

, #+/-<offset_12>

Immediate

post-indexed

[

<Rn>

]

, +/-<Rm>

Register

post-indexed

[

<Rn>

]

, +/-<Rm>, <shift> #<shift_imm>

Scaled register

post-indexed

Offset

or Pre or Post Memory Addressing (1/2)

example immediate offset-addressing:

LDR

R0, [R1, #12]

; R0

←

←

←

←

(R1 + 12)

R1

0x200

Base

Register

0x12

0x45

0x200

R0

0x12

Offset

12

0x20C

Offset-addressing modes

– the memory address is formed by adding or

subtracting an offset:

−

immediate offset / index

LDR

Rd, [<Rn>, #+/–<offset_12>]

; Rd

←

←

←

←

(Rn +/– offset_12)

−

register offset / index

LDR

Rd, [<Rn>, +/–<Rm>]

; Rd

←

←

←

←

(Rn +/– Rm)

−

scaled register offset / index

LDR

Rd, [<Rn>, +/–<Rm>, Barrel_shifter #<shift_imm>]
; Rd

←

←

←

←

(Rn +/–Barrel_shifter <Rm, shift_imm>)

Offset or

Pre

or

Post

Memory Addressing (2/2)

Pre-indexed

:

LDR

R0, [R1, #12] ! ; R0

←

←

←

←

(R1 + 12)

; if cc = true then R1 = R1 + 12

0x12

R1

0x200

Base

Register

0x45

0x200

R0

0x12

Offset

12

0x20C

Post-indexed

:

LDR

R0, [R1], #12

; R0

←

←

←

←

(R1)

; if cc = true then R1 = R1 + 12

0x5

R1

0x200

Original

Base Register

0x12

0x45

0x200

R0

0x45

Offset

12

0x20C

R1

0x20C

Updated

Base Register

R1

0x20C

Updated

Base Register

w

ri

te

b

a

c

k