DSCN5328 (2)

Synchroniczna pamięć DRAM (SDRAM)

* praca w trybie potokowym / z przeplotem (pipelined / interleaved)

Ord mar/ memory icctu

lAlfcBl ”0 o|A2l|B2™ D 0|a31|b3^| 0 OlAal^BaW 0 0]

One cycie for readmg out data from memory

Reduced access time

Bank ttructured memory access    O ^1    1 ■■    0 •

Ullt B1- D Dl

*■——ł--——W-!

Bank 1    |A2    62 ^| D O

Bank 2    |A3 ^

Bank 3    |A4 B4

Bank 4

The timing «s shifted to contro* tfte overtappng

address «put and data output paths.    ⁸ⁿ ***"" waftcaoon

for raduced memory access tirnes

Fig 2 Companson of ortknary memory access and interleaved memory access