6551263146

cadence

Digital Verification Engineer

KATOWICE / WARSZAWA

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Digital Verification Engineer will be responsible for pre-silicon RTL verification of błock, subsystem and top level. With deep understanding of SOC architecture and meticulous attention to details, the individual will interact with all disciplines to develop reusable test bench and verification environment deploying the latest methodology with metric driven verification.

As part of the System Design Enablement team at Cadence in Europę, the Digital Verification Engineer will work closely with SoC architects and design engineers, deploying Cadence technology in demanding customer projects, creating leading edge MPSoCs for automotive, networking, and loT markets.

The candidate should have:

•    Degree in Electrical Engineering or Computer Science

•    Good understanding of digital design and verification flows from Spec2Gates

•    Excellent knowledge of hardware description and verification languages (e.g., SV, V)

•    Previous experience with state-of-art verification approaches and tools (e.g., UVM, MDV, formal approaches, software-driven verification, ...)

•    Strong motivation to learn quickly Cadence verification tools, flows and methodologies

•    Working knowledge of UNIX/Linux, shells, programming and scripting

•    Good communication skills and ability to work remotely

•    Team player (fluent in English)

•    Willingness to travel across Europę and work with customers

Are you looking for continued professional development? Do you want to create Solutions that will influence the development of technology and the shape of the world around you? If so, join our team!

Apply to: [e-mail]

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