1

Podstawy techniki

mikroprocesorowej

ETEW006

Architektura procesorów

Andrzej Stępień

Katedra Metrologii Elektronicznej i Fotonicznej

Struktura mikrokontrolera

Kontroler przerwań

Kontroler DMA

CPU

wewnętrzna pamięć

ROM/Flash

wewnętrzna pamięć

ROM/Flash

Koprocesor

arytmetyczny

sterownik pola LCD

sterownik pola LCD

sterownik klawiatury

sterownik klawiatury

przetworniki

liczniki (RTC)

liczniki (RTC)

Interfejsy

pamięci zewnętrzne

pamięci zewnętrzne

G

e

n

e

ra

to

ry

t

a

k

tu

ją

c

e

G

e

n

e

ra

to

ry

t

a

k

tu

ją

c

e

wewnętrzna pamięć

RAM

wewnętrzna pamięć

RAM

M

a

g

is

tr

a

le

MCU, µ

µ

µ

µ

C, Embedded System

first

computer system on a chip optimised for

control applications - microcontroller was
the

Intel 8048

(MCS-48, modified

Harvard architecture) released in 1975, with both RAM and ROM on the
same chip – this chip would find its way into Roland ProMars analog
synthesizers, over one billion PC keyboards, and other numerous
applications.

microcontroller

(also microcomputer, MCU or µC) can be considered a

self-contained system with a processor, memory and peripherals and can
be used with an embedded system.

embedded system

is a computer system designed to perform one or a

few dedicated functions often with real-time computing constraints
(portable devices such as digital watches and MP3 players)

http://en.wikipedia.org/wiki/Microcontroller

sequential nature of computers: an instruction is analyzed, data are
processed, the next instruction is analyzed, and so on

one shared memory for instructions (program) and data with one data bus and
one address bus between processor and memory

instructions and data have to be fetched in sequential order (known as the
Von Neuman Bottleneck), limiting the operation bandwidth

its design is simpler than that of the Harvard architecture (mostly used to
interface to external memory)

von Neumann Architecture

the same program and data bus

Program

&

Data

Memory

Program

&

Data

Memory

CPU

Data

Addr

von-NEUMANNA Architecture

Memory & I/O

addr1

addr2

addr3

Program

Memory

Data

Memory

memory mapped I/O

addr1

addr2

addr3

Program

&

Data

Memory

I/O

Harvard Architecture

different Program and Data Bus

Program

Memory

Program

Memory

Data

Memory

Data

Memory

uses physically separate memories for their instructions and data, each
type of memory is accessed via a separate bus

instructions and operands can therefore be fetched simultaneously,
instructions and data to be fetched in parallel

CPU

Data

Addr

Data

Addr

2

Harvard Architecture

Memory & I/O

Program

Memory

Program

Memory

addr1

addr2

Data

Memory

Data

Memory

addr3

addr4

isolated I/O

Program

or

Data

Memory

Program

or

Data

Memory

addr5

addr6

I/O

I/O

addr7

addr8

isolated Memory

Microprocessor & Microcontroller Mode

addr1

addr2

External

Program

Memory

Microprocessor

Mode

Internal

Program

Memory

addr4

Extended

Microcontroller

Mode

addr1

addr2

addr3

Internal

Program

Memory

addr4

Microcontroller

Mode

addr1

addr2

addr3

no

Program

Memory

External

Program

Memory

Memory

Memory

von-NEUMANN Architecture
MSP430

(1/2)

the same program and data bus

for code memory, data memory and SFR

CPU

Data

Addr

SFR

Data

Memory

Program

Memory

200h

0

0FFFFh

Reserved

16-bit

16-bit

BootLoader

0C00h

Reserved

MSP430x4xx Family. User’s Guide.

Texas Instruments, SLAU056J, January 2010

Special

Function

Registers

Special

Function

Registers

von-NEUMANN Architecture
MSP430

(2/2)

8-Bit

Peripheral

Modules

8-Bit

Peripheral

Modules

16-Bit

Peripheral Modules

16-Bit

Peripheral Modules

RAM

RAM

Reserved

Reserved

only

Byte

only

Byte

only

Word

Word/Byte

200h

100h

0

10h

The end address of RAM
depends on the amount of RAM
present and varies by device.

RAM can be used for both code
and data.

Bytes are located at even or
odd addresses

Words are only located at even
addresses

Low byte of a word is always an
even address

BootLoader

BootLoader

0C00h

Flash/ROM

Flash/ROM

Interrupt

Vector Table

Interrupt

Vector Table

Word/Byte

Word/Byte

0FFE0h

Flash/ROM

Flash/ROM

10000h

Word/Byte

Access

only

Word for CODE

Word/Byte for Data

Memory

Memory

von-NEUMANN Architecture
ARM7

the same program and data bus

for code memory, data memory and peripherals

CPU

Data

Addr

BootLoader

Data

Memory

Program

Memory

0x4000 0000

0

Reserved

32-bit

32-bit

Reserved

AHB

Peripherals

VPB

Peripherals

Reserved

for Extern

Memory

0x8000 0000

0xE000 0000

0xF000 0000

4 GB

UM10120. LPC2131/2/4/6/8 User manual.

Philips Semiconductors, Rev. 02 - 25 July 2006

Separated Memory

Separated Memory

HARVARD Architecture
C51

- Memory

(1/2)

the same program and data bus
for code memory, data memory and SFR

but another instructions

CPU

Data

Addr

SFR

Program

Memory

0FFh

0

0FFFFh

16-bit

8-bit

Extended

Program

Memory

Internal

Data

Memory

80h

Registers

External

Data

Memory

UM10344. P89LPC9151/9161/9171 User manual.

NXP Semiconductors, Rev. 01 - 7 January 2010

3

HARVARD Architecture
C51

- Memory

(2/2)

CODE

DATA

IDATA

IDATA

DATA

0

0

7Fh

80h

0FFh

SFR

RAM

rejestry

R

A

M

XDATA

wewnętrzna

pamięć

kodu

programu

zewnętrzna

pamięć

kodu

programu

zewnętrzna

pamięć
danych

wewnętrzna

pamięć
danych

0

segment

bitowy

EA

DATA

/

IDATA

/

XDATA

HARVARD Architecture
C51

- CODE & XDATA Memory

CODE

0

XDATA

zewnętrzna

pamięć

kodu

programu

zewnętrzna

pamięć
danych

wewnętrzna

pamięć
danych

0

EA

DATA / IDATA /

XDATA

adresowanie

pośrednie

(

@Ri, @DPTR

)

adresowanie
indeksowo-rejestrowo-pośrednie
(

@A+DPTR

)

adresowanie
natychmiastowe
(

#data

)

wewnętrzna

pamięć

kodu

programu

adresowanie

bezpośrednie

(

addr

)

HARVARD Architecture
C51

- DATA & IDATA Memory

SFR

SFR

RAM

RAM

DATA

IDATA

IDATA

DATA

0

7Fh

80h

0FFh

rejestry

R

A

M

segment

bitowy

DATA

/

IDATA

/ XDATA

adresowanie
rejestrowe (

Rn

)

adresowanie
pośrednie

(

@Ri

)

Oznaczenia

Bit

(BInary digiT) - pojedyncza, dwuwartościowa (binarna) jednostka

informacji o wartości 0 lub 1

Bajt

(Byte) - porcja informacji zawierająca (najczęściej) 8 bitów

Słowo

(Word) - porcja informacji, którą operuje jednostka centralna,

zawiera zwykle całkowitą liczbę bajtów, np. 16, 32 itp.

MSB

(Most Significant Bit/Byte) - bit/bajt najbardziej znaczący

(starszy)

LSB

(Least Significant Bit/Byte) - bit/bajt najmniej znaczący

(młodszy)

prefix:

1 K

= 2

10

(1.024)

1 k

= 10

3

(1.000)

1 M

= 2

20

(1.048.576) lub 10

6

(1.000.000)

BIT ⇔

⇔

⇔

⇔ BYTE

:

1 Kb

= 2

10

bitów (1.024 bity)

1 KB

= 2

10

bajtów (1.024 bajty)

Little / Big Endian Machines

0

7

N

Word

8

15

N+1

High Byte

Low Byte

Low Byte

High Byte

N

N+1

N+2

N−1

Little Endian:

memory address:

0

7

N+1

Word

8

15

N

High Byte

Big Endian:

High Byte

N

N+1

N+2

N−1

Low Byte

memory address:

Low Byte

Endianness

24547010.pdf
IA-32 Intel





 Architecture.

Software Developer’s Manual.
Volume 1: Basic Architecture

0

15

N

Word

Low
Byte

N+1

High
Byte

8 7

0

15

N

Doubleword

Low Word

16

31

N+2

High Word

0

N

Quardword

Low Doubleword

31

32

N+4

High Doubleword

63

0

N

Double Quardword

Low Quardword

63

64

N+8

High Quardword

127

32-bit microprocessor

ARM core

word

halfword

0

N

Byte

Byte

7

Steve Furber: ARM System-on-chip Architecture.

Secon edition. Addison-Wesley, 2000