1

Podstawy techniki

mikroprocesorowej

ETEW006

Przetworniki A/C i C/A

Andrzej Stępień

Katedra Metrologii Elektronicznej i Fotonicznej

AD Converter Resolution

Kester W.:

Data Converter Codes—Can You Decode Them.

(MT-009

TUTORIAL) Analog Devices, Rev.A, 10/08

Full–Scale

(FS) is independent of the number of bits of resolution (N)

integer binary can be interpreted as fractional binary if all integer
values are divided by 2

N

, for example:

−

MSB (most significant bit) has a weight of ½ (i.e., 2

(N–1)

/2

N

= 2

–1

),

−

next bit has a weight of ¼ (i.e., 2

–2

), and so forth down to the LSB

−

LSB (least significant bit) has a weight of 1/2

N

when the weighted bits are added up

, they form a number with any of

2

N

values, from 0 to

(1 – 2

–N

) of full-scale

1LSB = FS/2

N

AD Converter Resolution
Ideal Unipolar Transfer Function

Kester W.:

Data Converter Codes—Can You Decode Them.

(MT-009

TUTORIAL) Analog Devices, Rev.A, 10/08

FS

1 LSB

AD Converter Resolution
Ideal Bipolar Transfer Function

Kester W.:

Data Converter Codes—Can You Decode Them.

(MT-009

TUTORIAL) Analog Devices, Rev.A, 10/08

FS

1 LSB

Offset binary

, the zero signal

value is assigned the code 1000
(sequence of codes is identical
to that of straight binary)

Ones complement

can also be

used to represent negative
numbers (it is much less popular
than twos complement and
rarely used today)

Twos complement

is

identical to offset binary
with the most-significant-
bit (MSB) complemented
(inverted)

Successive Approximation ADC
Algorithm

Kester W.: ADC Architectures II: Successive Approximation ADCs.

(MT-021 TUTORIAL) Analog Devices, Rev.A, 10/08

U

X

?

U

X

= 13 V

FS

= 16 V, N = 4, 1LSB = FS/2

N

= 1 V

i = 3

U

3

(MSB) = 1/2

N - i

∗

FS = 8 V,

U

X

≥≥≥≥

(U

3

)

= 8

U

3

=

1

i = 2

U

2

= 1/2

N - i

∗

FS = 4 V,

U

X

≥≥≥≥

(U

3

+ U

2

)

= 12

U

2

=

1

i = 1

U

1

= 1/2

N - i

∗

FS = 2 V,

U

X

<

(U

3

+ U

2

+ U

1

)

= 14

U

1

= 0

i = 0

U

0

(LSB) = 1/2

N - i

∗

FS = 1 V,

U

X

≥≥≥≥

(U

3

+ U

2

+

U

1

+ U

0

) = 13

U

0

=

1

? = 11

0

1

3-Bit Switched Capacitor
SAR ADC

High Speed Data Conversion Overview.

Analog Devices, 2006, Section 1

If S1, S2, S3, and S4 are
all connected to ground,
a voltage equal to

–A

IN

appears at node A

Connecting S1 to

V

REF

adds a voltage equal to

V

REF

/2 to

–A

IN

Comparator then makes
the MSB bit decision,
and the SAR either
leaves S1 connected to

V

REF

or connects it to ground depending on the

comparator output (which is high or low depending on whether the voltage at
node

A

is negative or positive, respectively)

Similar process is followed for the remaining two bits: at the end of the
conversion interval, S1, S2, S3, S4, and SIN are connected to

A

IN

, S

C

is

connected to ground, and the converter is ready for another cycle

V

REF

A

IN

A

2

Dual—Slope Integrating ADC
Algorithm

Bryant J., Kester W.: ADC Architectures VIII: Integrating ADCs.

(MT-021 TUTORIAL) Analog Devices, Rev.A, 10/08

Figure 1: Dual Slope Integrating ADC

Dual—Slope Integrating ADC
Rejection of Noise Frequencies

Bryant J., Kester W.: ADC Architectures VIII: Integrating ADCs.

(MT-021 TUTORIAL) Analog Devices, Rev.A, 10/08

Figure 3: Frequency Response of Integrating ADC

excellent

rejection of

50-Hz & 60-Hz

STM8S
AD Converter

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics. December 2009, Doc ID 14587 Rev 6

10-bit resolution

Single and continuous
conversion modes

Programmable
prescaler: f

MASTER

divided by 2 to 18

External trigger option
using external interrupt
(ADC_ETR) or timer
trigger (TRGO)

Analog zooming (in
devices with V

REF

pins)

Interrupt generation at End of Conversion

Buffered continuous conversion mode (Data buffer size 10x10 / 8x10 bits)

Scan mode for single and continuous conversion

Sprzeczności konstrukcyjne

precyzyjna struktura przetwornika A/C pracuj

ą

ca z napi

ę

ciami na bardzo

małym poziomie, np.:

napi

ę

cie

warto

ść

1 LSB dla rozdzielczo

ś

ci

wzorcowe

V

REF

[V]

8 bitów

10 bitów

12 bitów

14 bitów

16 bitów

24 bity

[mV]

[mV]

[

µµµµ

V]

[

µ

V]

[

µ

V]

[nV]

5,0

19,6

4,89

1221

306

76,3

298

3,3

12,9

3,23

806

201

50,4

197

2,5

9,77

2,44

610

152

38,1

149

1,8

7,03

1,76

439

110

27,5

107

1,5

5,86

1,47

366

91,6

22,9

89,4

1,2

4,69

1,17

293

73,2

18,3

71,5

0,8

3,12

0,781

195

48,8

12,2

47,7

szybko działaj

ą

ca struktura cyfrowa z napi

ę

ciami o poziomie kilka rz

ę

dów

wy

ż

szymi od cz

ęś

ci analogowej, V

CC

= 0,8 .. 5,5 V

Offset

&

Gain Errors

Kester W.: The Importance of Data Converter Static Specifications

Don't Lose Sight of the Basics!

(MT-010 TUTORIAL) Analog Devices, Rev.A, 10/08

Figure 4: Bipolar Data Converter Offset and Gain Error

Offset

&

Gain Errors

Kester W.: The Importance of Data Converter Static Specifications

Don't Lose Sight of the Basics!

(MT-010 TUTORIAL) Analog Devices, Rev.A, 10/08

Figure 5: Method of Measuring Integral Linearity Errors

(Same Converter on Both Graphs)

3

Voltage Reference

MODEL

Output

Voltage

Temperature Long-Term

Supply

voltage

accuracy

coefficient

stability

Current

[V]

[ppm/°C]

[ppm]

[

µ

A]

1) ADR440B

2.048

±

1 mV

±

1

±

50

3mA

ADR444B

4.096

(25°)

2) MAX6138

2.048 / 4.096

±

0.1%

±

25

±

120

45

TYP

3) LM4132

2.048 / 4.096

±

0.05%

±

10

±

50

60

4) REF5020I

2.048

±

0.05%

±

3

800

REF5040I

4.096

(25°)

1. ADR440. Ultralow Noise, LDO XFET Voltage References with Current Sink and Source.

Analog Devices, 2008, D05428-0-3/08, Rev. C

2. MAX6138. Shunt Voltage Reference with Multiple Reverse Breakdown Voltages.

Maxim, 2004, Rev 2; 4/04

3. LM4132. SOT-23 Precision Low Dropout Voltage Reference.

National Semiconductor, DS201513, August 2006

4. REF50xx Low-Noise, Very Low Drift, Precision VOLTAGE REFERENCE

Texas Instruments SBOS410D, REVISED APRIL 2009

Sample

&

Hold

R

S

R

I

C

I

N-bitowy przetwornik
analogowo-cyfrowy

K

V

S

t

V

CI

= V

S

(1 - e )

V

S

t

SAMPLE

<

1

/

2

LSB

(R

S

+ R

I

)

∗

C

I

t

t

S

(

1

/

2

LSB) = (R

S

+ R

I

)

∗

C

I

∗

ln(2

∗

2

N

)

ln(2

∗

2

N

)

N

6,24

8

7,62

10

9,01

12

10,40

14

11,76

16

17,33

24

t

HOLD

+ t

CONVERSION

przykład:

N = 12 bitów
R

I

= 2 k

Ω

Ω

Ω

Ω

C

IMAX

= 40 pF

R

S

= 10 k

Ω

Ω

Ω

Ω

t

SAMPLE

≥≥≥≥

4,33

µµµµ

s

Wymagania Sample

&

Hold

programowalny (zmienny) czas próbkowania t

SAMPLE

mała rezystancja wej

ś

ciowego MPX i kluczy układu S&H

mała pojemno

ść

wej

ś

ciowa C

I

układu S&H

mała stratno

ść

kondensatora pami

ę

taj

ą

cego C

I

krótki czas przetwarzania ze wzgl

ę

du na upływno

ść

kondensatora

pami

ę

taj

ą

cego C

I

małe pr

ą

dy wej

ś

ciowe

Cortex-M3
STM32F101xx

STM32F101x6, STM32F101x8 STM32F101xB.

STMicroelectronics, Rev. 7, May 2008

R

AIN

maximum external impedance

allowed for an error below

1

/

4

of LSB (N = 12, from 12-bit resolution)

R

AIN

<

f

ADC

∗

C

ADC

∗

ln

(

2

N+2

)

T

S

– R

ADC

f

ADC

ADC clock frequency:

0.6 – 14 MHz

C

ADC

Internal sample and hold capacitor: < 5 pF

R

ADC

Sampling switch resistance:

< 1 k

Ω

Cortex-M3
LPC176x

LPC1768/66/65/64. 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB

SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN. NXP, Rev. 02-01, 17 February 2009

12-bit successive approximation ADC, 1 MHz conversion rate

Input multiplexing among 8 pins.

Power-down mode.

Individual channels can be selected for conversion.

Burst conversion mode for single or multiple inputs.

Optional conversion on transition of input pin or Timer Match signal.

Individual result registers for each ADC channel to reduce interrupt overhead.

DMA support

<tbd>

STM8S105xx
Some

ADC Parameters

STM8S105xx. Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,

integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C.

STMicroelectronics, June 2009 Doc ID 14771 Rev 8

f

ADC

ADC clock frequency

V

DDA

= 2.95 to 5.5 V

1

MIN

4

MAX

MHz

V

DDA

= 4.50 to 5.5 V

1

6

MHz

V

DDA

Analog supply

3

5.5

V

V

REF+

Positive reference voltage

2.75

V

DDA

V

V

REF-

Negative reference voltage

V

SSA

0.5

V

C

ADC

Internal sample and hold capacitor

3

TYP

pF

t

STAB

Wakeup time from standby

7

µ

s

t

CONV

Total conversion time (including sampling time
10-bit resolution)

f

ADC

= 4 MHz

3.5

µ

s

f

ADC

= 6 MHz

2.33

µ

s

14

1/f

ADC

|ET|

Total unadjusted error

f

ADC

= 2 MHz

1

2.5

LSB

f

ADC

= 6 MHz

1.6

3.5

LSB

|EO|

Offset error

f

ADC

= 2 MHz

0.6

2

LSB

f

ADC

= 6 MHz

1.2

2.5

LSB

|EG|

Gain error

f

ADC

= 2 MHz

0.2

2

LSB

f

ADC

= 6 MHz

0.8

2.5

LSB

|ED|

Differential linearity error

f

ADC

= 2 MHz

0.7

1.5

LSB

f

ADC

= 6 MHz

0.8

1.5

LSB

|EL|

Integral linearity error

f

ADC

= 2 MHz

0.6

1.5

LSB

f

ADC

= 6 MHz

0.6

1.5

LSB

A

D

C

a

c

c

u

ra

c

y

:

R

A

IN

<

1

0

k

Ω

V

D

D

A

=

5

V

4

MSP430FG4618
Some

ADC Parameters

12-bit ADC parameters (V

CC

= 2.2 – 3 V)

PARAM

TEST /CONDITIONS

MIN NOM MAX

UNIT

t

Sampling

Sampling time / R

S

= 400

Ω

, R

I

= 1000

Ω

,

1220

ns (3V)

C

I

= 30pF,

τ

= [R

S

+ R

I

] x C

I

1440

ns (2.2V)

Approximately ten Tau (

τ

) are needed to get an error of less than ±0.5 LSB:

t

Sample

= ln(2

n+1

)

∗

(R

S

+ R

I

)

∗

C

I

+ 800 ns

where n = ADC resolution = 12, R

S

= external source resistance

E

I

Integral linearity error / 1.4 V

≤

Ve

REF+

≤

1.6 V

±2

LSB

1.6 V < Ve

REF+

≤

V

AVCC

±1.7

LSB

E

D

Differential linearity error / C

VREF+

= 10

µ

F (tantalum)

and 100nF (ceramic)

±1

LSB

E

O

Offset error / Internal impedance of source R

S

< 100

Ω

C

VREF+

= 10

µ

F (tantalum) and 100nF (ceramic)

±2

±4

LSB

E

G

Gain error / C

VREF+

= 10

µ

F (tantalum) & 100 nF (ceramic)

±1.1

±2

LSB

E

T

Total unadjusted error / C

VREF+

= 10

µ

F (tantalum)

and 100nF (ceramic)

±2

±5

LSB

MSP430xG461x. MIXED SIGNAL MICROCONTROLLER

Texas Instruments, SLAS508G, REVISED OCTOBER 2007

Odczyt 12-bitowego

wyniku przetwarzania (1/2)

bit

11

bit

10

bit

9

bit

8

bit

7

bit

6

bit

5

bit

4

bit

3

bit

2

bit

1

bit

0

-

-

-

-

bit

11

bit

10

bit

9

bit

8

bit

7

bit

6

bit

5

bit

4

bit

3

bit

2

bit

1

bit

0

lub

-

-

-

-

MSByte

LSByte

Low Byte

High Byte

N

N+1

N+2

N

−

1

Little Endian

memory

address:

Big Endian

High Byte

N

N+1

N+2

N

−

1

Low Byte

memory

address:

Odczyt 12-bitowego

wyniku przetwarzania (2/2)

bit

11

bit

10

bit

9

bit

8

bit

7

bit

6

bit

5

bit

4

bit

3

bit

2

bit

1

bit

0

CH

3

CH

2

CH

1

CH

0

ADCDATAH (MSByte)

addr = 0DAh

ADCDATAL (LSByte)

addr = 0D9h

channel selection

bits

channel result

ADuC812

(Analog Devices)

C8051F00x

(CYGNAL Integrated Products)

bit

11

bit

10

bit

9

bit

8

bit

7

bit

6

bit

5

bit

4

bit

3

bit

2

bit

1

bit

0

x

x

x

x

ADC0H (MSByte)

addr = 0BFh

ADC0L (LSByte)

addr = 0BEh

channel result

sign extension of ADC0H.3
if a differential reading

otherwise = 0000b

ADLJST = 0

:

bit

11

bit

10

bit

9

bit

8

bit

7

bit

6

bit

5

bit

4

bit

3

bit

2

bit

1

bit

0

0

0

0

0

channel result

ADLJST = 1

ADuC812. MicroConverter, Multichannel 12-Bit ADC with Embedded Flash MCU.

Analog Devices, 2003

C8051F00x/1/2/5/6/7. Mixed-Signal 32KB ISP FLASH MCU Family.

Silicon Laboratories, 2003, Rev. 1.7 11/03

STM8S
AD Converter Data alignment

ADC_DRH

– ADC data register high (Address offset: 0x04)

ADC_DRL

– ADC data register low (Address offset: 0x05)

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics. December 2009, Doc ID 14587 Rev 6

Right Alignment

Left Alignment

D9 D8

D3 D2 D1 D0

D5 D4

D7 D6

ADC_DRH

ADC_DRL

D9 D8

D3 D2

D5 D4

D7 D6

D1 D0

ADC_DRH

ADC_DRL

Jak napisać program w C ?

[1/2]

C576

(Philips Semiconductors)

ADC0H (MSByte)

addr = 0AAh

ADC0L (LSByte)

addr = 09Ah

bit

9

bit

8

bit

7

bit

6

bit

5

bit

4

bit

3

bit

2

bit

1

bit

0

0

0

0

0

channel result

0

0

ADC1H (MSByte)

addr = 0ABh

ADC1L (LSByte)

addr = 09Bh

ADC2H (MSByte)

addr = 0ACh

ADC2L (LSByte)

addr = 09Ch

ADC5H (MSByte)

addr = 0AFh

ADC5L (LSByte)

addr = 09Fh

..................................................

................................................

Devices should not be used for new designs!
This product has been discontinued

83C576/87C576. 80C51 8-bit microcontroller family.

Philips Semiconductors, Jun 04, 1998

Jak napisać program w C ?

[2/2]

ADC Data Register

(ADDR – RW, undefined)

–

LPC213x

ADC Global Data Register

(AD0GDR, AD1GDR)

–

LPC214x

Converter0: AD0DR - 0xE003 4004

Converter0: AD1DR - 0xE006 0004

contains the ADC’s

DONE

bit and (when DONE is 1) the 10-bit result of the

most recent A/D conversion

ADDR / ADGDR

(ADC Data Register):

15

0

DATA

5

? ? ? ? ?

6

x x x x x x

x x x x

? ? ? ?

? ? ? ?

? ? ? ?

0

0 ? ?

16

23

24

26

31

?

DONE

while ( ! (ADDR & 0x8000 0000));
result = (ADDR & (0x3FF << 6)) >> 6;

UM10120. LPC2131/2/4/6/8 User manual.

NXP, Rev. 02 - 25 July 2006

5

ATmega8

The

ADC

features a

noise canceler

that enables conversion during sleep

mode to reduce noise induced from the CPU core and other I/O
peripherals. The noise canceler can be used with ADC Noise Reduction
and Idle mode. To make use of this feature, the following procedure should
be used:

Make sure that the ADC is enabled and is not busy converting.

Single

Conversion mode must be selected and the ADC conversion
complete interrupt must be enabled

.

Enter ADC Noise Reduction mode (or Idle mode).

The ADC will start a

conversion once the CPU has been halted

.

If no other interrupts occur before the ADC conversion completes, the

ADC interrupt will wake up the CPU

and execute the ADC

Conversion Complete interrupt routine.

ATmega8. 8-bit with 8K Bytes In-System Programmable Flash.

Atmel 2002, Rev. 2486H–AVR–09/02

ATmega8
PCB

Analog Noise Canceling Techniques

:

Keep

analog signal paths as short

as

possible. Make sure analog tracks run
over the analog ground plane, and

keep

them

well

away from high-speed

switching digital tracks

.

A

VCC

pin on the device should be

connected to the digital

VCC supply

voltage via an LC network

Use

ADC noise canceler

function to reduce induced noise from the CPU

If any ADC port pins are used as

digital outputs

, it is essential that these

do

not switch while a conversion is in progress

ATmega8. 8-bit with 8K Bytes In-System Programmable Flash.

Atmel 2002, Rev. 2486H–AVR–09/02

100nF

10

µ

A

n

a

lo

g

G

ro

u

n

d

P

la

n

e

MSP430
PCB

MSP430xG461x. MIXED SIGNAL MICROCONTROLLER

Texas Instruments, SLAS508G, REVISED OCTOBER 2007

Digital Power

Supply Decoupling

Analog Power

Supply Decoupling

Using an External

Positive Reference

Using the Internal

Reference Generator

Using an External

Negative Reference

Cortex-M3
STM32F101xx

STM32F101x6, STM32F101x8 STM32F101xB.

STMicroelectronics, Rev. 7, May 2008

Figure 29. Power supply and reference

decoupling
(V

REF

+ not connected to V

DDA

)

Figure 30. Power supply and reference

decoupling
(V

REF

+ connected to V

DDA

)

PCB

Power

Ground

Route

Embedded

Advantages:

–

Signal traces shielded and protected

–

Lower impedance, lower emissions and
crosstalk

Disadvantages:

–

Difficult prototyping and troubleshooting

–

Decoupling may be more difficult

Power

Ground

Route

not Embedded

Route

Op Amp Applications. Hardware and Housekeeping Techniques.

Chapter 7. Analog Devices. Analog Dialogue, Volume 39, 2005

PCB

Figure 2. When low noise precautions

are not taken during circuit design
and board layout, a 12-bit ADC
system under-performs with
approximately 5.45-bit accuracy (or
5.45 Effective Number of Bits).

Figure 3. If low noise, active and

passive devices are used, a ground
plane is included, by-pass
capacitors are added and a low-
pass (anti-aliasing) filter is placed
in the signal path. The code width
of 1024 samples is equal to one.

Bonnie C. Baker: Techniques that Reduce System Noise in ADC Circuits.

Microchip Technology, Analog Design Note ADN007

6

Multi—Slope ADCs

(1/3)

R

1

C

V

CC

t

V

C

V

CC

Phase 1

t

1

= –R

2

∗

C

∗

ln = N

∗

t

CLK

V

C

R

2

K

2

K

1

Charge

C

K1 - ON
K2 - OFF

V

REF

Phase 2

Discharge

C

K1 - OFF
K2 - ON

t

1

V

REF

V

CC

N = –R

2

∗∗∗∗

C

∗∗∗∗

f

CLK

∗∗∗∗

ln

V

REF

V

CC

MSP430x4xx Family. User’s Guide. Mixed Signal Products.

Texas Instruments SLAU056C, 2003

Multi—Slope ADCs

(2/3)

R

1

C

V

CC

t

V

C

V

CC

Phase 1

V

C

R

2

K

2

K

1

Charge

C

K1 - ON
K2 - OFF
K4 - OFF

V

REF

Phase 2

Discharge

C

K1 - OFF
K2 - ON
K4 - OFF

t

1

–R

4

∗

C

∗

f

CLK

∗

ln

V

REF

V

CC

R

4

K

4

Phase 3

Charge

C

K1 - ON
K2 - OFF
K4 - OFF

Phase 4

Discharge

C

K1 - OFF
K2 - OFF
K4 - ON

t

4

–R

2

∗

C

∗

f

CLK

∗

ln

V

REF

V

CC

N

4

N

2

=

N

4

N

2

R

4

= R

2

Multi—Slope ADCs

(3/3)

To get a resolution of N bits, the capacitor C must have a minimum capacity:

–2

N

R

XMIN

∗∗∗∗

f

CLK

∗∗∗∗

ln

C >

V

REFMAX

V

CC

f

CLK

measurement frequency in Hertz

R

XMIN

lowest resistance of sensor or reference resistor in Ohms

V

REFMAX

maximum value for threshold voltage V

REF

in Volts

MSP430
GPIO

&

Comparator

Temperature Measurement System

MSP430x4xx Family. User’s Guide. Mixed Signal Products.

Texas Instruments SLAU056C, 2003

Figure 1: 1-Bit DAC:

Changeover
Switch (Single-
Pole, Double
Throw, SPDT)

Simplest DAC Architectures

Kester W.: Basic DAC Architectures I: String DACs and Thermometer (Fully Decoded)

DACs. Analog Devices, 2008, MT-014 TUTORIAL, Rev.A, 10/08

R-2R Network DAC
Architectures

Figure 5: Voltage-Mode R-2R Ladder Network DAC

7

12-bit DA Converters

C8051F00x

D

11

D

10

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

-

-

-

-

D

11

D

10

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

-

-

-

-

1xx

010

D

11

D

10

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

-

-

-

-

000

DAC0L (0D2h)
DAC1L (0D5h)

DAC0H (0D3h)
DAC1H (0D6h)

DACx

DACx

V

DD

DACxEN

.....

.....

V

REF

Data is latched into DAC0 after a write to the corresponding DAC0H
register, so the write sequence should be DAC0L followed by DAC0H if the
full 12-bit resolution is required.

C8051F00x/1/2/5/6/7. Mixed-Signal 32KB ISP FLASH MCU Family.

Silicon Laboratories, 2003, Rev. 1.7 11/03

12-bit DA Converters

C8051F00x - Dynamic Performance

C8051F00x/1/2/5/6/7. Mixed-Signal 32KB ISP FLASH MCU Family.

Silicon Laboratories, 2003, Rev. 1.7 11/03

Voltage Output Slew Rate

Load = 40pF

0.44

TYP

V/

µ

s

Output Settling Time To ½ LSB

Output swing from code
0xFFF to 0x014

10

TYP

µ

s

Startup Time

DAC Enable asserted

10

TYP

µ

s

CURRENT CONSUMPTION (each DAC)

Power Supply Current (AV+
supplied to DAC)

Data Word = 0x7FF

110

TYP

400

MAX

µ

A

PWM

(1/2)

V

C

t

τ

T

0,

0

≤

t < T -

τ

V

C

,

T -

τ ≤

t < T

U(t) =

U(t)

{

Warto

ść

ś

rednia: U

sr

=

T

1

U(t) dt = V

C

∗

∫

0

T

T

τ

PWM

(2/2)

B = 0

B = 1

B = 2

B = 3

B = 4

B = 5

B = 6

B = 7

A0 A1 A2

C0 C1 C2

Licznik

B0

B1

B2

A < B

R

e

je

s

tr

P

W

M

komparator

C = 0

A = 0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

Licznik

Komparator

DPM - Distributed Pulse Modulation

np. P82C150 SLIO (Philips)

C = 0

A = 0

1

4

2

2

3

6

4

1

5

5

6

3

7

7

B = 0

B = 1

B = 2

B = 3

B = 4

B = 5

B = 6

B = 7

A0 A1 A2

C0 C1 C2

Licznik

B0

B1

B2

A < B

R

e

je

s

tr

P

W

M

komparator

Licznik

Komparator

Źródło prądowe

zmienne obci

ąż

enie R

VAR

i rezystor wzorcowy R

REF

warto

ść

pr

ą

du obci

ąż

enia I

L

:

programowa modulacja szeroko

ś

ci impulsów aby V

AC

= V

COMPREF

I

L

=

∗

V

CC

R

REF

R

2

R

1

+ R

2

we A/C

wy PWM

V

CC

AV

REF

AV

SS

V

SS

COMPREF

+

–

R

REF

R

VAR

R

2

R

1

8

4-wire touch screen

consists of

two

transparent resistive
layers

separated by

insulating spacers

Touch

Screen

Controller

TSC2008. Micro TOUCH SCREEN CONTROLLER with SPI.

Texas Instruments, SBAS406B, Rev MARCH 2009

4-wire touch screen

panel

works

by applying a

voltage across

the

vertical

or

horizontal resistive network

A/D converter converts

the

voltage measured

at the point where the

panel is

touched

Touch Screen Controller

Figure 25. Simplified Diagram of Single-

Ended Reference

measurement

of the current

Y position

of the pointing device is

made by connecting:

−

X+ input to the A/D converter

,

−

turning on Y+ and Y– drivers

and

digitizing voltage on X+

in

some applications

,

external

capacitors

may be required across

the touch screen to filter noise picked
up by the touch screen (that is,

noise

generated by the LCD panel or
backlight circuitry

) - these

capacitors provide a low-pass filter to
reduce the noise

Touch Screen Controller

standard

SPI bus

V

CC

= 1.2V to 3.6V