LABORATORIUM UKŁADÓW PROGRAMOWALNYCH
Projekt w języku VHDL do implementacji w układzie Xilinx (…)
Grupa: E1T1S1 Ocena
Wykonali: Anna Ambroziak Artur Kaczmarek
SPRAWOZDANIE
Temat: Pełzający wąż z użyciem wyświetlaczy 7-segmentowych.

1. Założenia projektowe.

2. Kod

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mod11 is

Port ( CLK : in STD_LOGIC;

R : in STD_LOGIC;

Q : inout STD_LOGIC_VECTOR (3 downto 0);

W1 : inout STD_LOGIC_VECTOR(7 downto 0);

W2 : inout STD_LOGIC_VECTOR (7 downto 0));

end mod11;

architecture Behavioral of mod11 is

begin

process (CLK, R)

begin

if R='1' then Q<=(others=>'0');

elsif rising_edge(CLK) then Q<=Q+1;

end if;

if Q= "0000" then W1<="00011111"; W2<="11111111";--13,2,5

end if;

if Q= "0001" then W1<="10001111"; W2<="11111111";-- 2,5,1

end if;

if Q= "0010" then W1<="11000111"; W2<="11111111";-- 5, 1, 7

end if;

if Q= "0011" then W1<="11100111"; W2<="11101111";-- 1, 7, 80

end if;

if Q= "0100" then W1<="11110111"; W2<="11001111";-- 7, 80, 72

end if;

if Q= "0101" then W1<="11111111"; W2<="10001111";-- 80, 72, 81

end if;

if Q= "0110" then W1<="11111111"; W2<="00011111";-- 72, 81, 82

end if;

if Q= "0111" then W1<="11111111"; W2<="00111101"; -- 81, 82, 84

end if;

if Q= "1000" then W1<="11111111"; W2<="01110101"; -- 82, 84 ,79

end if;

if Q= "1001" then W1<="11111101"; W2<="11110101"; -- 84, 79,11

end if;

if Q= "1010" then W1<="01111101"; W2<="11110111"; -- 79,11,13

end if;

if Q= "1011" then W1<="00111101"; W2<="11111111"; -- 11, 13, 2

end if;

if Q= "1100" then Q<="0000";

end if;

end process;

end Behavioral;