3-wejściowa bramka NAND entity nand3 is port(a,b,c : in bit; y : out bit); end nand3; architecture a1 of nand3 is begin y <= not(a and b and c); end a1; Przerzutnik T wyzwalany zboczem narastajacym, z wejsciem zerujacym entity fft is port (T,C,R : in bit; Q : out bit); end fft; architecture a1 of fft is begin process (C,R) variable tq : bit; if R = ′1′ then tq := ′0′; elsif C′event and C = ′1′ and T = ′1′ then tq := not tq; end if; Q <= tq; end process; end a1; Zastosowanie sygnału wewnętrznego - inny opis architektury przerzutnika T architecture a2 of fft is signal tp : std_logic; begin process (C,R) begin if R = ′1′ then tp <= ′0′; elseif C′event and C = ′1′ then tp <= tp xor T; end if; end process; Q <= tp; end a2; Przerzutnik T z wyjsciem buffer entity fft1 is port (T,C,R : in bit; Q : buffer bit); end fft1; architecture a1 of fft1 is begin process (C,R) begin if R = ′1′ then Q <= ′0′; elsif C′event and C = ′1′ and T = ′1′ then Q <= not Q; end if; end process; end a1; Przerzutnik D entity ffd is port(D,C,R : in bit; Q : out bit); end ffd; architecture a1 of ffd is begin process(C,R) begin if R = ′1′ then Q <= ′0′ ; elsif (C′event and C = ′1′) then Q <= D; end if; end process; end a1; Multipleksera 2-na-1 architecture a4 of mux2_1 is begin y <= a when s = ′0′ else b; end a4; albo std_logic architecture a5 of mux2_1 is begin y <= a when s = ′0′ else b when s = ′1′ else ′X′; end a5; multiplekser 4-na-1 entity muxg8_4_1 is port (a,b,c,d : in std_logic_vector(7 downto 0); adr : in std_logic_vector(1 downto 0); y : out std_logic_vector(7 downto 0)); end muxg8_4_1; architecture a1 of muxg8_4_1 is begin with adr select y <= a when ″00″, b when ″01″, c when ″10″, d when ″11″, ″XXXXXXXX″ when others; end a1; Przerzutnika D przy uzyciu instrukcji wait on architecture a2 of ffd is begin process begin wait on (R,C); if R = ′1′ then Q <= ′0′; elsif (C′event and C = ′1′) then Q <= D; end if; end process; end a2;

„CASE” Na przykład, jeśli c jest liczbą całkowitą i y jest sygnałem out typu std_logic case c is when 1 | 3 | 4 | 14 => y <= ′1′; when 2 | 5 | 6 => y <= ′0′; when 7 | 9 => y <= ′X′; when others => null; end case; while-loop Na przykład można opisać wirtualny zegar, który działa tylko wtedy gdy zmienna boolowska flaga ma wartość true: process begin while flaga loop zegar <= not zegar; wait for okres_zegara/2; end loop; end process; FUNKCJE Przykład funkcji komparacji trzech bitów: function komp3(a,b,c : std_logic) return boolean is begin if ((a xor b) nor (a xor c)) = ′1′ then return true; else return false; end if; end komp3; Podobną rolę pełni typ unsigned, ale tylko w odniesieniu do operacji arytmetycznych. function vec_int(signal a : std_logic_vector) return integer is variable p : integer; begin p := 0; for i in a′range loop p := p * 2; case a(i) is when ′1′ | ′H′ => p := p + 1; when others => null; end case; end loop; return p; end vec_int; Tester parzystości wektora A o automatycznie rozpoznawalnej długości i generujący dwa sygnały wyjściowe: P (gdy liczba jedynek jest parzysta) i N (gdy jest odwrotnie). procedure test_par( signal A : in std_logic_vector; signal P,N : out std_logic) is variable t : std_logic; begin t := ′1′; for i in A′range loop t := t xor A(i); end loop; P <= t; N <= not t; end test_par; Przerzutnik JK wyzwalany zboczem narastającym, z asynchronicznym zerowaniem i ustawianiem procedure FFJK1 (signal C,J,K,R,S : in std_logic; signal Q : inout std_logic; signal QN : out std_logic) is variable JK : std_logic_vector(0 to 1); variable re : boolean; begin JK := J & K; re := rising_edge(C); if R = ′1′ then Q <= ′0′; elsif S = ′1′ then Q <= ′1′; elsif re then case JK is when ″10″ => Q <= ′1′; when ″01″ => Q <= ′0′; when ″11″ => Q := not Q; when others => null; end case; end if; QN <= not Q; end FFJK1; Do opisu przerzutnika JK można wykorzystać jego logiczne równanie funkcyjne: procedure FFJK2 (signal C,J,K,R,S : in std_logic; signal Q : inout std_logic; signal QN : out std_logic) is variable re : boolean; begin re := rising_edge(C); if R = ′1′ then Q <= ′0′; elsif S = ′1′ then Q <= ′1′; elsif re then Q <= (J and not Q) or (not K and Q); end if; QN <= not Q; end FFJK2; Uniwersalna procedura dla rejestru równoległego procedure reg (signal C,R : in std_logic; signal D : in std_logic_vector; signal Q : out std_logic_vector) is variable ff : boolean; begin ff := rising_edge(C); if R = ′1′ then Q <= (Q′range => ′0′); elsif ff then Q <= D; end if; end reg;

Rejestry równoległe Można wykorzystać model przerzutnika D i zamienić typ sygnałów wejściowych i wyjściowych ze skalarnego na złożony - Rejestr n-bitowy entity regn is generic (n : positive := 8); port (C,R : in std_logic; D : in std_logic_vector(n-1 downto 0); Q : out std_logic_vector(n-1 downto 0)); end regn; architecture a1 of regn is begin process (R, C) begin if R = ′1′ then Q <= (others => ′0′); elsif rising_edge(C) then Q <= D; end if; end process; end a1; Sieć bramek i rejestr RA-zerowanie asynchroniczne RS-zerowanie synchroniczne entity siec is port (C,RA,RS : in std_logic; D : in std_logic_vector(4 downto 0); Q : out std_logic_vector(3 downto 0)); end siec; Sieć bramek i rejestr -- opis klasyczny (bez użycia procedury) architecture a1 of siec is begin p0: process begin if RA = ′1′ then Q(0) <= ′0′; else wait until rising_edge(C); Q(0) <= D(0) xor D(1); end if; end process p0; p1: process(C,RA) begin if RA = ′1′ then Q(1) <= ′0′; elsif rising_edge(C) then Q(1) <= D(2) and not D(3); end if; end process p1; p2: process begin wait until rising_edge(C); Q(2) <= not(D(0) or D(4) or RS); end process p2; p3: process(C) begin if rising_edge(C) then if RS = ′1′ then Q(3) <= ′0′; else Q(3) <= D(2) and D(4); end if; end if; end process p3; end a1; Sieć bramek i rejestr -- opis z użyciem procedury Proces p3 można zapisać krócej, stosując opis logiczny p3: process(C) begin if rising_edge(C) then Q(3) <= (not RS) and D(2) and D(4); end if; end process p3; procedure regr (signalC : in std_logic; signal R,D : in std_logic_vector; signal Q : out std_logic_vector) is variable rr : boolean; begin rr := rising_edge(C); for i in R′range loop if R(i)= ′1′ then Q(i) <= ′0′; elsif rr then Q(i) <= D(i); end if; end loop; end regr; Konwerter kodu Przykład procedury opisujacej konwerter kodu 1-z-10 na kod BCD8421 (koder) procedure conv_to_BCD( signal ten : in std_logic_vector(9 downto 0); signal bcd : out std_logic_vector(3 downto 0)) is begin case ten is when ″0000000010″ => bcd <= ″0001″; when ″0000000100″ => bcd <= ″0010″; when ″0000001000″ => bcd <= ″0011″; when ″0000010000″ => bcd <= ″0100″; when ″0000100000″ => bcd <= ″0101″; when ″0001000000″ => bcd <= ″0110″; when ″0010000000″ => bcd <= ″0111″; when ″0100000000″ => bcd <= ″1000″; when ″1000000000″ => bcd <= ″1001″; when others => bcd <= ″0000″; end case; end conv_to_BCD;

Pięciobitowy licznik synchroniczny z przeniesieniami równoległymi Będą użyte dwa komponenty: czterowejściowa bramka AND i przerzutnik T. -- czterowejsciowa bramka AND - komponent library ieee; use ieee.std_logic_1164.all; entity and4 is port (A,B,C,D : in std_logic; Y : out std_logic); end and4; architecture a1 of and4 is begin y <= a and b and c and d; end a1; Komponent przerzutnika T library ieee; use ieee.std_logic_1164.all; entity fft is port (T,C,R : in std_logic; Q : out std_logic); end fft; architecture a1 of fft is begin process(C,R) variable tt : std_logic; begin if R = '1' then tt := '0'; elsif rising_edge(C) then tt <= tt xor T; end if; Q <= tt; end process; end a1; Licznik library ieee; use ieee.std_logic_1164.all; --use work.pak.all; gdy komponenty sa w pakiecie pak entity licznik5 is port(CL,RA : in std_logic; Q : out std_logic_vector(4 downto 0)); end licznik5; architecture struktura of licznik5 is component and4 port (A,B,C,D : in std_logic := ′1′; Y : out std_logic); end component; component fft port (T,C,R : in std_logic; Q : out std_logic); end component; signal T,QL : std_logic_vector(4 downto 0); Multiplekser 4-na-1 entity mux4 is port (a,b,c,d : in std_logic); adr : in std_logic_vector(1 downto 0); y : out std_logic); end mux4; architecture a1 of mux4 is begin with adr select y <= a when ″00″, b when ″01″, c when ″10″, d when others; -- albo: d when ″11″; end a1; Multiplekser Przykład opisu w stylu przepływowym, logicznym architecture a2 of mux4 is begin y <= a and (not adr(0)) and (not adr(1)) or b and adr(0) and (not adr(1)) or c and (not adr(0)) and adr(1) or d and adr(0) and adr(1); end a2; Multiplekser - W opisie procedury (styl behawioralny) należy użyć instrukcji sekwencyjnej case-is-when: procedure mux4 ( signal a,b,c,d : in std_logic; signal adr : in std_logic_vector(1 downto 0); signal y : out std_logic) is begin case adr is when ″00″ => y <= a; when ″01″ => y <= b; when ″10″ => y <= c; when others => y <= d; -- albo when ″11″ => y <= d; end case; end mux4; Sieć bramek i rejestr - parametry aktualne library ieee; use ieee.std_logic_1164.all; use work.pak.all; entity siec is port (C,RA,RS : in std_logic; D : in std_logic_vector(4 downto 0); Q : out std_logic_vector(3 downto 0)); end siec; architecture a2 of siec is signal w,z : std_logic_vector(3 downto 0); begin w(0) <= D(0) xor D(1); w(1) <= D(2) and not D(3); w(2) <= not(D(0) or D(4) or RS); w(3) <= (not RS) and D(2) and D(4); z <= (′0′,′0′,RA,RA); regr(C,z,w,Q); end a2;

Komparator Jednobitowy komparator można opisać funkcją XNOR: entity komp1 is port(p,q : in std_logic; y : out std_logic); end komp1; architecture a1 of komp1 is begin y <= p xnor q; end a1; procedure komp ( signal P : in std_logic_vector; signal Q : in std_logic_vector; y : out std_logic) is begin if P = Q then y <= '1' else y <= '0'; end if; end komp; Licznik synchroniczny z przeniesieniami szeregowymi library IEEE; use IEEE.std_logic_1164.all; entity ffg is port (e1,e2,e3,C,R : in std_logic; Q : out std_logic; T : inout std_logic); end ffg; architecture a1 of ffg is signal tt : std_logic; begin T <= e1 and e2 and e3; process (C,R) begin if R = '1' then tt <= '0'; elsif rising_edge(C)then tt <= tt xor T; end if; end process; Q <= tt; end a1; Licznik synchroniczny z przeniesieniami szeregowymi „z generic” library IEEE; use IEEE.std_logic_1164.all; entity licz is generic (N : positive := 8); port(CL,RA,EN : in std_logic; Q : out std_logic_vector(N-1 downto 0)); end licz; architecture gener of licz is component ffg port (e1,e2,e3,C,R : in std_logic; Q : out std_logic; T : inout std_logic); end component; signal TL,QL : std_logic_vector(N-1 downto 0); begin G0: ffg port map (e1=>EN,e2=>'1',e3=>'1',C=>CL, R=>RA,T=>TL(0), Q=>QL(0)); G1: for i in 1 to N-1 generate -- powielanie G2: ffg port map (e1=>EN,e2=>QL(i-1),e3=>TL(i-1),C=>CL,R=>RA,T=>TL(i), Q => QL(i)); end generate; Q <= QL; end gener; Dzielnik częstotliwości przez 10 z symetrycznym przebiegiem wyjściowym entity dzielnik_10 is port(ck: instd_logic; y : outstd_logic); end dzielnik_10; architecture a1 of dzielnik_10 is signal stan : std_logic_vector (3 downto 0); begin process (ck) begin if rising_edge(ck) then case stan is when "1011" => stan <= "011X"; when "011X" => stan <= "010X"; when "010X" => stan <= "000X"; when "000X" => stan <= "0010"; when "0010" => stan <= "0011"; when "0011" => stan <= "111X"; when "111X" => stan <= "110X"; when "110X" => stan <= "100X"; when "100X" => stan <= "1010"; when "1010" => stan <= "1011"; when others => stan <= "1011"; end case; end if; end process; y <= stan(3); end a1; Automat o czterech stanach -detektor sekwencji stanów 01-01-10 entity auto4 is port (X : in std_logic_vector(1 downto 0); ck : in std_logic; y : out std_logic); end auto4; architecture b2 of auto4 is type stan is (S1, S2, S3, S4); signal S : stan; begin process (ck, S) begin if rising_edge(ck) then case S is when S1 => y <= '0'; if X = "01" then S <= S2; else null; end if; when S2 => y <= '0'; if X = "01" then S <= S3; else S <= S1; end if; when S3 => y <= '0'; if X = "10" then S <= S4; elsif X = "01" then S <= S3; else S <= S1; end if; when S4 => y <= '1'; if X = "01" then S <= S2; else S <= S1; end if; end case; end if; end process; end b2;

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