library ieee;
use ieee.std_logic_1164.all;
a
entity port_mode is port(
a, b : in stdjogic; x, y : out stdjogic
end port_mode;
architecture datajlow of port_mode is
signal tmp: std_logic; |
begin
tmp <= a and b; x <= tmp y <= not tmp; end datajlow;
Mariusz Rawski