Zad 1
entity mux5a is
port(a, b, c, d, e : in std_logic;
EN:in std_logic ;
adres : in std_logic_vector(2 downto 0);
y : out std_logic);
end mux5a;
architecture a1 of mux5a is
begin
process(adres, EN, a, b, c, d, e)
begin
if EN='1' then
case adres is
when "000"=> y <= a;
when "001"=> y <= b;
when "010"=> y <= c;
when "011"=> y <= d;
when "100"=> y <= e;
when others=> y <= 'X';
end case;
else y<= '0';
end if;
end process;
end a1;
Zad 2
entity mux5_2 is
port (a, b, c, d, e :in std_logic;
EN, OE : in std_logic;
adres : in std_logic_vector(2 downto 0);
y : out std_logic);
end mux5_2;
architecture a1 of mux5_2 is
begin
process(a, b, c, d, e, EN, OE, adres)
begin
if OE='1' then
if EN='1' then
case adres is
when "000" => y <= a;
when "001" => y <= b;
when "010" => y <= c;
when "011" => y <= d;
when "100" => y <= e;
when others => y <= 'X';
end case;
else y <= '0';
end if;
else y <= 'Z';
end if;
end process;
end a1;
Zad 3
entity dmux_6 is
port(wej, EN, OE : in std_logic;
adres : in std_logic_vector(2 downto 0);
wyj : out std_logic_vector(5 downto 0));
end dmux_6;
architecture a1 of dmux_6 is
begin
process (wej, adres, EN, OE)
begin
if EN='1' then
if OE='1' then
case adres is
when "000" => wyj <= "00000" & wej;
when "001" => wyj <= "0000" & wej & '0';
when "010" => wyj <= "000" & wej & "00";
when "011" => wyj <= "00" & wej & "000";
when "100" => wyj <= '0' & wej & "0000";
when "101" => wyj <= wej & "00000";
when others => wyj <= "XXXXXX";
end case;
else wyj <="ZZZZZZ";
end if;
else wyj <="XXXXXX";
end if;
end process;
end a1;
Zad 4
entity mux8 is
port (a,b,c,d,e,f,g,h : in std_logic_vector (7downto 0);
adres : in bit_vector (2 downto 0);
y : out std_logic_vector (7 downto 0));
end mux8;
architecture a1 of mux8 is
begin
with adres select
y<= a when "000",
b when "001" ,
c when "010" ,
d when "011" ,
e when "100" ,
f when "101" ,
g when "110" ,
h when "111" ;
end a1;
Zad 5a
entity dekoder_10_4 is
port (wej : in std_logic_vector(3 downto 0);
EN : in std_logic;
wyj : out std_logic_vector(9 downto 0));
end dekoder_10_4;
architecture a1 of de koder_10_4 is
begin
process (wej, EN)
begin
if EN='1' then
case wej is
when "0000" => wyj <= "0000000001";
when "0001" => wyj <= "0000000010";
when "0010" => wyj <= "0000000100";
when "0011" => wyj <= "0000001000";
when "0100" => wyj <= "0000010000";
when "0101" => wyj <= "0000100000";
when "0110" => wyj <= "0001000000";
when "0111" => wyj <= "0010000000";
when "1000" => wyj <= "0100000000";
when "1001" => wyj <= "1000000000";
when others => wyj <= "XXXXXXXXXX";
end case;
else wyj <= "0000000000";
end if;
end process;
end a1;
Zad 5b
entity koder_10_4 is
port (wej : in std_logic_vector(9 downto 0);
EN : in std_logic;
wyj : out std_logic_vector(3 downto 0));
end koder_10_4;
architecture a1 of koder_10_4 is
begin
process (wej, EN)
begin
if EN='1' then
case wej is
when "0000000001" => wyj <= "0000";
when "0000000010" => wyj <= "0001";
when "0000000100" => wyj <= "0010";
when "0000001000" => wyj <= "0011";
when "0000010000" => wyj <= "0100";
when "0000100000" => wyj <= "0101";
when "0001000000" => wyj <= "0110";
when "0010000000" => wyj <= "0111";
when "0100000000" => wyj <= "1000";
when "1000000000" => wyj <= "1001";
when others => wyj <= "XXXX";
end case;
else wyj <= "0000";
end if;
end process;
end a1;
Zad 6
entity koder_10_4 is
port (wej : in bit_vector(9 downto 0);
EN : in std_logic;
wyj : out std_logic_vector(3 downto 0));
end koder_10_4;
architecture a1 of koder_10_4 is
signal wzor : bit_vector (9 downto 0) :="1111111111";
begin
process (wej, EN)
variable wynik : bit;
variable tt : integer;
begin
for i in 9 downto 0 loop
wynik := wzor(i) XNOR wej(i);
tt:=i;
if wynik='1' then exit;
end if;
end loop;
if EN='1' then
case tt is
when 0 => wyj <= "0000";
when 1 => wyj <= "0001";
when 2 => wyj <= "0010";
when 3 => wyj <= "0011";
when 4 => wyj <= "0100";
when 5 => wyj <= "0101";
when 6 => wyj <= "0110";
when 7 => wyj <= "0111";
when 8 => wyj <= "1000";
when 9 => wyj <= "1001";
when others => wyj <= "XXXX";
end case;
else wyj <= "0000";
end if;
end process;
end a1;
Zad 8
entity komp is
port (P,Q :in std_logic_vector (7 downto 0);
R,M,W: out std_logic);
end komp;
architecture a1 of komp is
begin
process (P,Q)
begin
R <='0';
M <='0';
W <= '0';
if P>Q then W<='1';
elsif P=Q then R<='1';
else M<='1';
end if;
end process;
end a1;
Zad 9
entity tester_sek is
port(wej: in std_logic_vector (7 downto 0);
wyj :out std_logic );
end tester_sek;
architecture a1 of tester_sek is
begin
wyj<=(((((((wej(0) xor wej(1)) xor wej(2)) xor wej(3))
xor wej(4)) xor wej(5)) xor wej(6)) xor wej(7));
end a1;
Zad 10
entity sumator4 is
port( a, b: in std_logic_vector (3 downto 0);
ci: in std_logic ;
s: out std_logic_vector (3 downto 0);
co : out std_logic );
end sumator4;
architecture a1 of sumator4 is
signal c1,c2,c3: std_logic ;
begin
s(0)<= a(0) xor b(0) xor ci;
c1<= (a(0) and b(0)) or (ci and (a(0) xor b(0)));
s(1)<= a(1) xor b(1) xor c1;
c2<= (a(1) and b(1)) or (c1 and (a(1) xor b(1)));
s(2)<= a(2) xor b(2) xor c2;
c3<= (a(2) and b(2)) or (c2 and (a(2) xor b(2)));
s(3)<= a(3) xor b(3) xor c3;
co<= (a(3) and b(3)) or (c3 and (a(3) xor b(3)));
end a1;
Zad 11
entity sr is
port (s,r:in std_logic ;
q :inout std_logic );
end sr;
architecture a1 of sr is
begin
process (s,r,q)
begin
if (s and r)='0' then
q<=(not s nand (not r nand q));
else q<='X';
end if;
end process ;
end a1;
Zad 12a
entity sr is
port (s,r:in std_logic ;
q :inout std_logic );
end sr;
architecture a1 of sr is
begin
process (s,r,q)
begin
if (s and r)='0' then
q<=s or (q and (not r));
else q<='X';
end if;
end process ;
end a1;
Zad 12b
entity sr is
port (s,r:in std_logic ;
q :inout std_logic );
end sr;
architecture a1 of sr is
begin
process (s,r,q)
begin
if (s and r)='0' then
q<=(r nor (s nor q));
else q<='X';
end if;
end process ;
end a1;
Zad 13
entity zatrzask_D is
port (D, C, R : in std_logic;
Q : inout std_logic);
end zatrzask_D;
architecture a1 of zatrzask_D is
begin
process(C, R, D)
begin
if R='1' then Q <= '0';
else Q <= (C and D) or (not C and Q);
end if;
end process;
end a1;
Zad 15
entity rejestr is
port(D, CK, SE : in std_logic;
wyj : inout std_logic_vector (7 downto 0) :="00000000");
end rejestr;
architecture a1 of rejestr is
begin
process(SE, CK, D)
begin
if (SE='1' and falling_edge(CK)) then
wyj <= D & wyj(7 downto 1);
else null;
end if;
end process;
end a1;
Zad 16
entity przerzutnik_D is
port (D, CLK, EN : in std_logic;
Q : inout std_logic);
end przerzutnik_D;
architecture a1 of przerzutnik_D is
begin
process(CLK, EN)
begin
if rising_edge(CLK) then
Q <= (D and EN) or (not EN and Q);
else null;
end if;
end process;
end a1;
Zad 17
entity procedura_rejestr is
port (CK, DS, SE : in std_logic;
wyj : inout std_logic_vector(7 downto 0));
end procedura_rejestr;
architecture a1 of procedura_rejestr is
----------------------------------------
procedure rejestr_przesuw (signal D, CLK, EN : in std_logic;
signal Q : inout std_logic_vector) is
variable n : integer;
begin
n := Q'length;
if EN='1' and rising_edge(CLK) then
Q <= D & Q (n-1 downto 1);
else null;
end if;
end rejestr_przesuw;
----------------------------------------
begin
process(CK, SE)
begin
rejestr_przesuw(D => DS, CLK => CK, EN => SE, Q => wyj);
end process;
end a1;
Zad 20
use IEEE.std_logic_unsigned.all;
entity licznik is
generic(n : positive :=4);
port (CE, CK, M, RST : in std_logic;
Q : inout std_logic_vector(n-1 downto 0));
end licznik;
architecture a1 of licznik is
begin
process(CK)
begin
if RST='1' then
for i in Q'range loop
Q(i) <='0';
end loop;
else
if M='1' then
if (CE='1' and rising_edge(CK)) then
Q <= Q + 1;
else null;
end if;
else
if (CE='1' and rising_edge(CK)) then
Q <= Q - 1;
else null;
end if;
end if;
end if;
end process;
end a1;
Zad 21
use IEEE.std_logic_unsigned.all;
entity licznik is
generic(n : positive :=4);
port (CE, CK, M, RST : in std_logic;
Q : inout std_logic_vector(n-1 downto 0));
end licznik;
architecture a1 of licznik is
--------------------------------
procedure licznik (signal zegar, zerowanie, zezwolenie, kierunek : in std_logic;
signal wyjscie : inout std_logic_vector) is
begin
if zerowanie='1' then
for i in wyjscie'range loop
wyjscie(i) <='0';
end loop;
else
if kierunek='1' then
if (zezwolenie='1' and rising_edge(zegar)) then
wyjscie <= wyjscie + 1;
else null;
end if;
else
if (zezwolenie='1' and rising_edge(zegar)) then
wyjscie <= wyjscie - 1;
else null;
end if;
end if;
end if;
end licznik;
--------------------------
begin
licznik(zegar => CK, kierunek => M, zerowanie => RST, zezwolenie => CE, wyjscie => Q);
end a1;
Zad 24
library ieee;
use ieee.std_logic_1164.all;
entity przt is
port (t, c, r : in std_logic ;
q:inout std_logic) ;
end przt;
architecture a1 of przt is
signal tt : std_logic ;
begin
process (c,r)
begin
if r='1' then tt<='0';
elsif rising_edge(c) then tt<= tt xor T;
end if;
end process;
q<= tt;
end a1;
---------------------------------------
library ieee;
use ieee.Std_logic_1164.all;
entity licz24 is
generic(n : positive :=8);
port (ce,cl, zegar : in std_logic ;
q : out std_logic_vector (n-1 downto 0));
end licz24;
architecture a1 of licz24 is
component przt
port (t,c,r : in std_logic ;
q :inout std_logic) ;
end component;
signal tl,ql, nql : std_logic_vector (n-1 downto 0);
begin
nql <=not ql;
g0: przt port map (t=>ce, c=>zegar, r=>cl, q=>ql(0));
g1: for i in 1 to n-1
generate
g2: przt port map(c=>nql(i-1), t=>'1', r=>cl, q=>ql(i));
end generate ;
q<=ql;
end a1;
2