Przykłady opisu układów w języku VHDL

Sumator jednobitowy

entity sumator_jednobitowy is

-- porty wejściowe i wyjściowe:

port ( ai, bi, ci in Bit ;

ci_1,si out Bit );

begin

assert (ai = „1”) and (bi = „1”) and (ci = „1”) report „przepełnienie sumatora”

severity MESSAGE;

end sumator;

Opis w języku VHDL - ciało strukturalne

architecture struktura of sumator_jednobitowy is

-- deklaracja sygnałów wewnętrznych

signal G: Bit_vector (1 to 5)

begin

-- struktura sumatora jednobitowego - konkretyzacja składników

Xor1: entity Work.xor_gate port map (A => ai,

B => bi,

D => G(1));

Xor2: entity Work.xor_gate port map (A => G(1),

B => ci,

D => si);

And1: entity Work.and_gate port map (A => ci,

B => bi,

D => G(3));

And2: entity Work.and_gate port map (A => ci,

B => ai,

D => G(4));

And3: entity Work.and_gate port map (A => bi,

B => ai,

D => G(5));

Or1: entity Work.or_gate port map (A => G(3),

B => G(4),

C => G(5),

D => ci_1);

end struktura;

Opis w języku VHDL - ciało behawioralne

architecture behavior of sumator_jednobitowy is

-- deklaracja sygnałów wewnętrznych

signal G: Bit_vector (0 to 1)

I: Bit_vector (0 to 2);

begin

P1: process (ai,bi,ci)

Begin

I(0) <= ai;

I(1) <= bi;

I(2) <= ci;

case I is

when „000” => G <= „00” after 5 ns;

when „001” => G <= „10” after 5 ns;

when „010” => G <= „10” after 5 ns;

when „011” => G <= „01” after 5 ns;

when „100” => G <= „10” after 5 ns;

when „101” => G <= „01” after 5 ns;

when „110” => G <= „01” after 5 ns;

when „111” => G <= „11” after 5 ns;

when others G <= „00”;

end case;

si <= G(0);

ci_1 <= G(1);

end process;

end behavior;

Opis w języku VHDL - ciało mieszane

architecture mixed_adder of sumator_jednobitowy is

-- deklaracja sygnałów wewnętrznych

signal G: Bit_vector (0 to 2));

begin

P1: process (ai,bi,ci);

begin

si <= ai xor bi xor ci after 5 ns;

end process;

And1: entity Work.and_gate port map (A => ci,

B => bi,

D => G(0));

And2: entity Work.and_gate port map (A => ci,

B => ai,

D => G(1));

And3: entity Work.and_gate port map (A => bi,

B => ai,

D => G(2));

Or1: entity Work.or_gate port map (A => G(0),

B => G(1),

C => G(2),

D => ci_1);

end mixed_adder;

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